eda技術(shù)與應(yīng)用講義第3章原理圖輸入設(shè)計(jì)方法quartusii版本(編輯修改稿)
2025-02-27 23:23 本頁(yè)面
【文章內(nèi)容簡(jiǎn)介】 he HIF data, the Database Builder copies each CNF into the project database. Each CNF is inserted into the database as many times as it is used within the original hierarchical project. The database thus preserves the electrical connectivity of the project. ? The Compiler uses this database for the remainder of project processing. Each subsequent Compiler module updates the database until it contains the fully optimized project. In the beginning, the database contains only the original lists。 at the end, it contains a fully minimized, fitted project, which the Assembler uses to create one or more files for device programming. ? As it creates the database, the Database Builder examines the logical pleteness and consistency of the project, and checks for boundary connectivity and syntactical errors (., a node without a source or destination). Most errors are detected and can be easily corrected at this stage of project processing. ? 返回 Logic Synthesizer ? The Compiler module that synthesizes the logic in a project39。s design files. ? Using the database created by the Database Builder, the Logic Synthesizer calculates Boolean equations for each input to a primitive and minimizes the logic according to your specifications. ? For projects that use JK or SR flipflops, the Logic Synthesizer checks each case to determine whether a D or T flipflop will implement the project more efficiently. D or T flipflops are substituted where appropriate, and the resulting equations are minimized accordingly. ? The Logic Synthesizer also synthesizes equations for flipflops to implement state registers of state machines. An equation for each state bit is optimally implemented with either a D or T flipflop. If no state bit assignments have been made, or if an inplete set of state bit assignments has been created, the Logic Synthesizer automatically creates a set of state bits to encode the state machine. These encodings are chosen to minimize the resources used. ? 返回 Fitter（適配器） ? The Compiler module that fits the logic of a project into one or more devices. ? Using the database updated by the Partitioner, the Fitter matches the logic requirements of the project with the available resources of one or more devices. It assigns each logic function to the best logic cell location and selects appropriate interconnection paths and pin assignments. ? The Fitter attempts to match any resource assignments made for the project with the resources on the device. If it cannot find a fit, the Fitter allows you to override some or all of your assignments or terminate pilation. ? The Fitter module generates a Fit File that documents pin, buried logic cell, chip, clique, and device assignments made by the Fitter module in the last successful pilation. Each time the project piles successfully, the Fit File is overwritten. You can backannotate the assignments in the file to preserve them in future pilations. ? 返回 Timing SNF Extractor(時(shí)序 SNF文件提取器 ) ? The Compiler module that creates a timing SNF containing the logic and timing
公司管理相關(guān)推薦
鄂ICP備17016276號(hào)-1