cmos制造工藝流程簡(jiǎn)介(編輯修改稿)
2025-02-27 20:34 本頁(yè)面
【文章內(nèi)容簡(jiǎn)介】 Strip Photoresist ? Ion Implantation 18 ? Photolithography ? Mask 8 pattern alignment and UV exposure ? Rinse away nonpattern PR ? Ion Implantation ? B+ ion bombardment ? 50 keV for 5 1013cm2 ? Strip Photoresist Extension (LDD) Formation PMOS 19 SiO2 隔離介 質(zhì)層 ? CVD or LPCVD Deposition of SiO2 ? Silane and Oxygen Or ? um ? Provides spacing between gate and sourcedrain. SiO2 Spacer Deposition 20 ? Photolithography ? Mask 6 oversized pattern alignment and UV exposure ? Rinse away nonpattern PR ? Vertical etch rate high ? Lateral etch rate low ? Strip Photoresist Anisotropic Spacer Etch ? Plasma Etch ? Anisotropic etch ? Flourine based 21 ? Screen Oxide Growth ? Thin SiO2 layer ~10 nm to scatter the implanted ions ? Photolithography ? Mask 9 pattern alignment and UV exposure ? Rinse away nonpattern PR ? Ion Implantation ? As+ ion bombardment ? 75 keV for 24 1015cm2 ? Strip Photoresist NMOS Source and Drain Implant 源漏區(qū)的形成 Arsenic ? Reduce channeling 22 ? Photolithography ? Mask 10 pattern alignment and UV exposure ? Rinse away nonpattern PR ? Ion Implantation ? B+ ion bombardment ? 510 keV for 13 1015cm2 ? Strip Photoresist PMOS Source and Drain Implant 23 ? N+ and P+ Drivein ? Thermal diffusion of dopant to shallower than desired depth ?Drivein is a cumulative process! ? Dry Furnace (N2 ambient) ? Anneal 30 min 900?C or RTA 60 sec 1000 ?C 1050 ?C Transient Enhanced Diffusion (TED 瞬 態(tài) 增強(qiáng) 擴(kuò) 散 ) ? Higher than normal diffusivity due to crystal damage Thermal Annealing ? Thermal Anneal ? Repair crystal lattice structure damage due to implantation 24 接觸與局部互聯(lián)的形成 Contacts and Interconnects ? Titanium sputtering local contacts ? Conformal Coat with SiO2 ? Planarization ? Tungsten Plug vias ? Aluminum Metal Deposition ? Repeat – Coat – Planarize – Plug – Metal deposition 25 ? HF etch to remove thin SiO2 ? Remove screen oxide from drain, source and ploy gate regions ? Dip (浸 ) for a few seconds with HF Contact Openings LDD and Sidewall structure ? NMOS: Lateral N+ N P N N+ ? PMOS: Lateral P+ P N P P+ 26 Titanium Deposition ? Ti is deposited by sputtering (typically 100 nm). ? Ti target hit with Ar+ ions in a vacuum chamber ? The Ti is reacted in an N2 ambient ? Forms TiSi2 and TiN (typically 1 min 600 700 ?C). ? TiSi2 has excellent contact characteristics (良好的 導(dǎo) 體 ) ? TiN does not, but can b
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