現(xiàn)代計(jì)算機(jī)體系結(jié)構(gòu)--cpu英文版(編輯修改稿)
2025-02-10 22:37 本頁面
【文章內(nèi)容簡介】 ruction fetch – E: Execute ? ALU operation with register input and output ? For load and store – I: Instruction fetch – E: Execute ? Calculate memory address – D: Memory ? Register to memory or memory to register operation 12 Effects of Pipelining 13 Optimization of Pipelining ? Delayed branch – Does not take effect until after execution of following instruction – This following instruction is the delay slot 14 Normal and Delayed Branch Address Normal Branch Delayed Branch Optimized Delayed Branch 100 LOAD X, rA LOAD X, rA LOAD X, rA 101 ADD 1, rA ADD 1, rA JUMP 105 102 JUMP 105 JUMP 106 ADD 1, rA 103 ADD rA, rB NOOP ADD rA, rB 104 SUB rC, rB ADD rA, rB SUB rC, rB 105 STORE rA, Z SUB rC, rB STORE rA, Z 106 STORE rA, Z 15 Use of Delayed Branch 16 Controversy ? Quantitative – pare program sizes and execution speeds ? Qualitative – examine issues of high level language support and use of VLSI real estate ? Problems – No pair of RISC and CISC that are directly parable – No definitive set of test programs
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