現(xiàn)代計(jì)算機(jī)體系結(jié)構(gòu)--cpu英文版(專(zhuān)業(yè)版)
【正文】 Slow code: LW Rb,b LW Rc,c ADD Ra,Rb,Rc SW a,Ra LW Re,e LW Rf,f SUB Rd,Re,Rf SW d,Rd Fast code: LW Rb,b LW Rc,c LW Re,e ADD Ra,Rb,Rc LW Rf,f SW a,Ra SUB Rd,Re,Rf SW d,Rd 30 Control dependences ? PC dependences 第 1 條 IF ID EX M EM WB第 2 條 IF ID EX M EM WB第 3 條 IF ID EX M EM WB第 5 條 IF ID EX M EM WB第 4 條 IF ID EX M EM WB第 1 條 IF ID EX M EM WB第 2 條 IF ID EX M EM WB第 3 條 IF ID EX M EM WB第 5 條 IF ID EX M EM WB第 4 條 IF ID EX M EM WB演講完畢，謝謝觀看！ 。1 本資料來(lái)源 2 CPU(1) 3 KEY POINTS 1. CISC RISC 2. Instruction pipeline 3. Instructionlevel parallelism 4. Dynamic scheduling 5. Scoreboard 6. Loop unrolling 7. Register renaming 8. Tomasulo’s approach 4 1 CISC RISC ? Why CISC (1)? ? Compiler simplification? – Disputed… – Complex machine instructions harder to exploit – Optimization more difficult ? Smaller programs? – Program takes up less memory but… – Memory is now cheap – May not occupy less bits, just look shorter in symbolic form ? More instructions require longer opcodes ? Register references require fewer bits 5 1 CISC RISC ? Why CISC (2)? ? Faster programs? – Bias
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