【文章內(nèi)容簡介】 _Buffer Uart_Buffer[NumberOfArray(serial_drv)]。/***************************************************************************\ 說明: s3c2410串口驅(qū)動程序for uCOSII\***************************************************************************/include include include include include ../inc/include ../inc///include ../inc/sys/include ..uhal/define UTRSTAT_TX_EMPTY (1 2)define UTRSTAT_RX_READY (1 0)define UART_ERR_MASK 0xF define ULCON_IR (1 6) /* use InfraRed mode */define fULCON_PAR Fld(3,3) /* what parity mode? */define ULCON_PAR FMsk(fULCON_PAR)define ULCON_PAR_NONE FInsrt(0x0, fULCON_PAR) /* No Parity */define ULCON_PAR_ODD FInsrt(0x4, fULCON_PAR) /* Odd Parity */define ULCON_PAR_EVEN FInsrt(0x5, fULCON_PAR) /* Even Parity */define ULCON_PAR_1 FInsrt(0x6, fULCON_PAR) /* Parity force/checked as 1 */define ULCON_PAR_0 FInsrt(0x7, fULCON_PAR) /* Parity force/checked as 0 */define ULCON_STOP (1 2) /* The number of stop bits */define ULCON_ONE_STOP (0 2) /* 1 stop bit */define ULCON_TWO_STOP (1 2) /* 2 stop bit */define fULCON_WL Fld(2, 0) /* word length */define ULCON_WL FMsk(fULCON_WL)define ULCON_WL5 FInsrt(0x0, fULCON_WL) /* 5 bits */define ULCON_WL6 FInsrt(0x1, fULCON_WL) /* 6 bits */define ULCON_WL7 FInsrt(0x2, fULCON_WL) /* 7 bits */define ULCON_WL8 FInsrt(0x3, fULCON_WL) /* 8 bits */define ULCON_CFGMASK (ULCON_IR | ULCON_PAR | ULCON_WL)define UCON_CLK_SEL (1 10) /* select clock for UART */define UCON_CLK_PCLK (0 10) /* PCLK for UART baud rate */define UCON_CLK_UCLK (1 10) /* UCLK for UART baud rate */define UCON_TX_INT_TYPE (1 9) /* TX Interrupt request type */define UCON_TX_INT_PLS (0 9) /* Pulse */define UCON_TX_INT_LVL (1 9) /* Level */define UCON_RX_INT_TYPE (1 8) /* RX Interrupt request type */define UCON_RX_INT_PLS (0 8) /* Pulse */define UCON_RX_INT_LVL (1 8) /* Level */define UCON_RX_TIMEOUT (1 7) /* RX timeout enable */define UCON_RX_ERR_INT (1 6) /* RX error status interrupt enable */define UCON_LOOPBACK (1 5) /* to enter the loopback mode */define UCON_BRK_SIG (1 4) /* to send a break during 1 frame time */define fUCON_TX Fld(2,2) /* function to write Tx data to the UART Tx buffer */define UCON_TX FMsk(fUCON_TX)define UCON_TX_DIS FInsrt(0x0, fUCON_TX) /* Disable */define UCON_TX_INT FInsrt(0x1, fUCON_TX) /* Interrupt or polling */define UCON_TX_DMA0 FInsrt(0x2, fUCON_TX) /* DMA0 request */define UCON_TX_DMA1 FInsrt(0x3, fUCON_TX) /* DMA1 request */define fUCON_RX Fld(2,0) /* function to read data from UART Rx buffer */define UCON_RX FMsk(fUCON_RX)define UCON_RX_DIS FInsrt(0x0, fUCON_RX) /* Disable */define UCON_RX_INT FInsrt(0x1, fUCON_RX) /* Interrupt or polling */define UCON_RX_DMA0 FInsrt(0x2, fUCON_RX) /* DMA0 request */define UCON_RX_DMA1 FInsrt(0x3, fUCON_RX) /* DMA1 request */define fUFCON_TX_TR Fld(2,6) /* trigger level of transmit FIFO */define UFCON_TX_TR FMsk(fUFCON_TX_TR)define UFCON_TX_TR0 FInsrt(0x0, fUFCON_TX_TR) /* Empty */define UFCON_TX_TR4 FInsrt(0x1, fUFCON_TX_TR) /* 4byte */define UFCON_TX_TR8 FInsrt(0x2, fUFCON_TX_TR) /* 8byte */define UFCON_TX_TR12 FInsrt(0x3, fUFCON_TX_TR) /* 12byte */define fUFCON_RX_TR Fld(2,4) /* trigger level of receive FIFO */define UFCON_RX_TR FMsk(fUFCON_RX_TR)define UFCON_RX_TR4 FInsrt(0x0, fUFCON_RX_TR) /* 4byte */define UFCON_RX_TR8 FInsrt(0x1, fUFCON_RX_TR) /* 8byte */define UFCON_RX_TR12 FInsrt(0x2, fUFCON_RX_TR) /* 12byte */define UFCON_RX_TR16 FInsrt(0x3, fUFCON_RX_TR) /* 16byte */define UFCON_TX_REQ (1 2) /* autocleared after resetting FIFO */define UFCON_RX_REQ (1 1) /* autocleared after resetting FIFO */define UFCON_FIFO_EN (1 0) /* FIFO Enable */define UMCON_AFC (1 4) /* Enable Auto Flow Control */define UMCON_SEND (1 0) /* when notAFC, set nRTS 1:39。L39。 0:39。H39。 level */define UTRSTAT_TR_EMP (1 2) /* 1: Transmitter buffer amp。 shifter register empty */define UTRSTAT_TX_EMP (1 1) /* Transmit buffer reg. is empty */define UTRSTAT_RX_RDY (1 0) /* Receive buffer reg. has data */define UERSTAT_BRK (1 3) /* Break receive */define UERSTAT_FRAME (1 2) /* Frame Error */define UERSTAT_PARITY (1 1) /* Parity Error */define UERSTAT_OVERRUN (1 0) /* Overrun Error */define UFSTAT_TX_FULL (1 9) /* Transmit FIFO is full */define UFSTAT_RX_FULL (1 8) /* Receive FIFO is full */define fUFSTAT_TX_CNT Fld(4,4) /* Number of data in Tx FIFO */define UFSTAT_TX_CNT FMsk(fUFSTAT_TX_CNT)define fUFSTAT_RX_CNT Fld(4,0) /* Number of data in Rx FIFO */define UFSTAT_RX_CNT FMsk(fUFSTAT_RX_CNT)define UMSTAT_dCTS (1 3) /* see Page 1116 */define UMSTAT_CTS (1 0) /* CTS(Clear to Send) signal */define UTXH_DATA 0x000000FF /* Transmit data for UARTn */define URXH_DATA 0x000000FF /* Receive data for UARTn */define UBRDIVn 0x0000FFFF /* Baud rate division value ( 0) *//* UBRDIVn = (int)(PCLK/(bsp * 16)1 or UBRDIVn = (int)(UCLK/(bsp * 1