(mips體系結(jié)構(gòu)剖析-編程與實(shí)踐)第4章-mips-異常和中斷處理文庫(編輯修改稿)
2024-08-31 06:50 本頁面
【文章內(nèi)容簡介】 sters: These two registers are mostly used by kernel as a temporary buffer to hold some values if necessary. So that you don39。t have to find some predefined memories for that purpose. One thing we should be careful is : When you are allowing the nested exception/interrupt handling, you need take care of these two registers39。 values as they will be overwritten, for example. I don39。t encouarge people to use the AT register too often, even though you can use the .set noat directive. I have found a bug in mipsgcc, which will use the AT register anyway, even after we use the .set noat. In other wrods, using AT is dangeous somhow if you are not quite familire with the register convention/usage流水線(Pipeline) and Interrupt Taken 我們知道，MIPS是一個RISC技術(shù)處理器。在某一個時(shí)刻，在流水線上，同時(shí)有若干個指令被處理在不同的階段(stage)上. MIPS處理器一般采用5級流水結(jié)構(gòu)。 IF RD ALU MEM WB 那么我們要問：當(dāng)一個Interrupt發(fā)生時(shí)，CPU到底該 如何handle？答案是這樣的： “On an interrupt in a typical MIPS CPU, the last instruction to be pleted before interrupt processing starts will be the one that has just finished its MEM stage when the interrupt is detected. The exception victim will be the one that has just finished its ALU stage... 對上述的理解是這樣的：CPU 會**完成**那條已**finish** MEM stage的指令。然后將exception victim定位在下一條(following)指令上。要注意的是：我們是在談Interrupt, not the exception. 在MIPS中，這是有區(qū)別的。 下面介紹幾個重要的SR(Status Register)與Exception和中斷有關(guān)的位。 * SR[EXL] Exception Level。 set by the processor when any exception other than Reset, Soft Reset, NMI, or Cache Error exception are taken. 0: normal 1: exception When EXL is set: Interrupts are disabled. 換句話說，這時(shí)SR[IE]位是不管用了，相當(dāng)于所有的中斷都被MASK了。 TLB refill exceptions will use the general exception vector instead of the TLB refill vector. EPC is not updated if another exception is taken. 這一點(diǎn)要注意。如果我們想支持nesting exceptions, 我們要在exce
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