北京聞亭公司tms320c620xx701系列超高速信號處理板及應(yīng)(編輯修改稿)
2025-08-14 13:27 本頁面
【文章內(nèi)容簡介】 Rate ? Compliant with a Variety of Standards ? Double Buffered Transmit, Triple Buffered Receive ? uLaw, ALaw panding ? Multichannel EMIF Overview ? High Throughput External Memory – 800 Mbytes/sec with 200 MHz SBSRAM ? 32Bit Wide ? Byte Addressable ? Supports Both Little and Big Endian ? Memory Types Supported – SDRAM – Synchronous Burst SRAM (SBSRAM) – Asynchronous ? 52 Mbytes Total External Address Reach ? 4 Chip Enable Spaces ? Supports Requests from – CPU Program Bus – CPU Data Ports – DMA DMA ? High Performance: 800Mbytes/sec Sustained – Can Read and Write 1 32bit word Every Cycle ? 5 Channels – 4 Programmable Channel – 5th Auxiliary Channel to Service HPI ? Event Synchronization ? Programmable Data Widths (8, 16, 32bits) ? Programmable priority ? Autoinitialization ? Programmable Addressing ? Emulation Mode ? Interrupt Generation to CPU ? Supports Either Little or Big Endian DMA Controller EMIF Internal Program Internal Data Internal Peripherals HPI AUX Channel 3 Channel 2 Channel 1 Channel 0 DMAC Status Pins ? Purpose: Moves Data in Background of CPU Operation ? Loosely Based on C3x/C32/C4x DMA Timers ? 2 32Bit Timers ? Similar to C3x/C4x Timers ? Separate Input and Output Pins ? Internal or External Clock Source ? Clock and Pulse Mode of Output ? Can Interrupt CPU DSP2621EA超高速信號處理板 ： D S P 2 6 2 1 E A 板 系統(tǒng)功能框圖S D R A M4 Mx 32 B i tS B S R A M 1 2 8 K X 3 2模擬信號兩路 高速 A / D 4 0 M 1 2 B i t 雙口 R A M 4 K X
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