【文章內(nèi)容簡介】 fier circuit, the circuit set the capacitor C4 is the role of negative feedback: RFCF is not large, lowfrequency signals will be fiction, virtually played the role of highpass filter, which with the previous RC lowpass filter needed to band together fiction outside the highfrequency noise signal and lowfrequency shaking signals at the same time by adjusting the value of C4,Get a different gain.In addition, R6, R15, R10, R22 four resistors form by the bipolar input op amp to convert a univocal input, in order to meet the requirements of ADchip unspooled input, input range can be +5 V ~ 5V. To adapt to most of the voltage sensor output characteristics. VM intervention voltage source, R93 access CH1 current source, can be adapted to current sensor, R85 and R14 for the protection of resistance. Unit Design and Implementation of ADC1．Select analogdigital conversion of basic technical indicators（1）Conversion time and the maximum sampling frequency ofSampling frequency chosen is too high will increase the amount of data and lead to followup analysis and processing workload increased dramatically. According to sampling theorem, the sampling frequency as long as the signal processing is greater than twice the highest frequency, we can not lose the information contained in the original signal. In practical work, generally selected, so that can determine the sampling interval, the analogdigital conversion modules, must be pleted within the sampling interval T conversion. Therefore, conversion time and the maximum sampling frequency of these two indicators is very important.（2）Conversion bitSelect the number of bits in the ADC, it is necessary according to its measurement range and accuracy required to determine the median conversion. The practical application of some of ADC, its end figures are not reliable, need to give up, so that measurement accuracy is reduced by half, this should be the choice when the ADC to be fully considered. Also, be sure to enable measurement of the signal through the opamp circuit, its voltage amplitude at the ADC within the scope of work.（3）Sample ChannelADC sampling channel is also able to input analog signals into large ones. In selecting analogdigital conversionDevice, we should take this into account, that is, parallel input channels simultaneously, or the order of the serial input.2．ADC cell design（1）ADC chip selectBased on the above choice of analogdigital conversion of basic technical indicators, data acquisition system used as the ADS8361 chip ADC module, ADS8361 is the production of It’s ADS8361 is a dualchannel, fourway, analog differential input, 16bit A / D conversion precision device。 it to be divided into two fourchannel differential inputs are connected to a standalone converter, and can plete pairs of signals collected at the same time, the maximum conversion rate of up to 500kHz, which 2μs pleting a second A / D sampling, sampling after the data from the serial access on the output. It operates in the 50kHz frequency has a strong antiinterference ability,Particularly suitable for high sampling rate data acquisition requirements of occasions, ADS8361 using SSOP24 package. In addition, ADS8361 also provides highspeed dual serial interface can be effective in reducing software overhead, and power consumption is very low, only 150mW. Shown in Figure 45, the chip ADS8361 has two internal samplehold devices. Allowed to enter the fourchannel differential signal with a internal reference voltage output (pin directly to the output + v), the input signal range is (if using the internal reference voltage, then the input signal range ~ + v) 4 analog input .The photo shows the pin diagram ,46 in which the chipselect signal, BGND digital manner, CLOCK is the clock input, CONVST pin is the A / D conversion pulse input pin, Ml, M0, A0 pin used to select sampling channel and data channels。 RD pin to read the data pins.The photo shows the pin diagram ,46 in which the chipselect signal, BGND digital manner, CLOCK is the clock input, CONVST pin is the A / D conversion pulse input pin, Ml, M0, A0 pin used to select sampling channel and data channels。 RD pin to read the data pins.Acquisition circuit works: VA + is positive that the output number, VAinverting signal output terminal for the REF for the reference voltage input, CD4053 access multiplexer switch。 ADS8361 The CS pin is the chip select terminal, Ml,M0, A0 pin used to select the sample channel and data channel。 RD pin to read the data pins, CONVST pin is the A / D conversion pulse, in use with the CONVST pin RD should be connected, CLOCK pin with the input sampling clock, DATAA, DATAB is the serial data output。 the other seven Lu acquisition signal [(VB +, VB), (VC +, VC), (VD +, VD), (VE +, VE), (VF +, VF), (VG +, VG), (VH +, VH)] the collection of the same principle with the