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st/ Idle 狀態(tài) : 進(jìn)入 Update IR狀態(tài)后 ,再使 TMS = 0 , 則進(jìn)入 Run Test/ Idle 狀態(tài) ,此時(shí) , IC進(jìn)入 HIGHZ 狀態(tài)。 (以上描述可用 VHDL代碼生成) JTAG 應(yīng)用 ? Infra test: Infrastructure to check if the Boundary Scan connections are correct. ? Inter test: Interconnections inbetween BoundaryScan ponents. ? Memory cluster test: test memory. ? Cluster test: Interconnections inbetween no BoundaryScan ponents. ? Flash Prog : FLASH programmer. ? PLD Prog : IC programmer. INFRA Notice yellow line 4 BoundaryScan :D3, D4, D5 and D6. Non BoundaryScan SRAM D1. Non BoundaryScan FLASH D2. Non BoundaryScan D7. INFRA (PASS) INFRA (PASS) ? CAPTURE Test The CAPTURE is a fixed value from the INSTRUCTION REGISTER. It is used to check the TDI TDO and the TCK and TMS connections. The FLAG is added to test the connection from TDI of the tester to the board. ? IDENT Test Optional IDENTETY REGISTER is checked to check if the correct chips are used. ? TRST Test To test the optional TRST signal. * If NO TRST CAPTURE is checked. * If TRST IDENTETY REGISTER is checked. INFRA ( PASS) INFRA ( Failure) INFRA ( Failure) BoundaryScan IC D6, D3 and D 5 are OK. * D4 and FLAG are BAD. Something wrong inbetween D6 and D4. INTER Notice green line INTER (PASS) Single line H = Drive value for a Boundary Scan output cell. L = Drive value for a Boundary Scan output cell. 1 = Sense value for a Boundary Scan input cell. 0 = Sense value for a Boundary Scan input cell. Z = Disabled Boundary Scan output cell. X = Sense value for a Boundary Scan input cell unknown. = No active Boundary Scan cells on the . INTER (Failure)