introductiontocadence(編輯修改稿)
2024-11-17 15:43 本頁面
【文章內(nèi)容簡介】 is also “THIN” at “vdd!” And “gnd!”, “CONT” is required to connect “THIN” and “Metal1”. Once the “THIN” exist, there is PPIMP or NPIMP. ? After finish drawing, do not fet to place pins on inputs and outputs. NTUEE 13 Useful Hotkeys ? Some useful hotkeys: – r: draw rectangular block – z/Z: room in and room out – k/K: ruler on/off – s:stretch – c: copy ? m: move ? u: undo ? Del: delete ? q:query ? p: create path NTUEE 14 LSW NTUEE 15 OptionDisplay NTUEE 16 OptionsEditor NTUEE 17 Online DRC NTUEE 18 HW1 (1)請用 CADENCE畫出 transmissiongate full adder的 Layout。 (2)此 Layout必須通過 ONLINE DRC check (3) Due on March 13 NTUEE 19 Open the extracted view and type shiftf, we can see the N/PMOS with the value of L/W. Select Cparasitics Getting Extracted View NTUEE 20 Extract Layout to Spice (I) ? For the analog artist, do the following 3 steps: 1. Open .cshrc and find the line: setenv CDS_Netlisting_Mode=Digital change “Digital” to “Analog” 2. Open .simrc and find the line: simNlpGlobalLibName=sample change “sample” to “analogLib” 3. In , change the capacitor model to “pcapacitor” change the transistor model to “pmos4” and “nmos4”. NTUEE 21 Extract Layout to Spice (II) ? For the di
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