外文翻譯---微處理器報(bào)告-其他專業(yè)(編輯修改稿)
2025-02-24 09:33 本頁面
【文章內(nèi)容簡介】 SER and CLR wipe the contents of an entire register at once. SBR and CBR, which set or clear multiple bits at a time, are aliases for ORI and ANDI, respectively. Initial Launch Includes Five Parts Atmel launched its AVR product line with four basic chips: the 90S1200, the ’2313, the ’4414, and the ’8515. The latter three devices are very similar, differing mainly in the amount of memory on the chip: 2K, 4K, or 8K of flash, with the amount of onchip SRAM and E2PROM also increasing. The runt of the litter, the 1200, has only 1K of flash memory, no SRAM, no peripherals, and a restricted instruction set. With neither SRAM nor an external bus, the 1200 must use onchip flash for data storage, which will slow execution considerably unless programmers can get by with juggling the register set alone. The 1200 are also the only chip in the family currently in production. In 1,000unit quantities, the 20pin 90S1200 sells for a paltry $. It’s not often that the number of data bits outnumbers the pins on the package, but Atmel managed to get close with its 1220 device, an 8pin version of the 1200. After power, ground, and crystal connections, only four pins are free for I/O. Most AVR chips e in 20pin DIP or SOIC packages, which provide access to more I/O lines。 only in a 40pin package do the chips bond out their address and data buses for access to external memory. All the parts are fabricated on Atmel’s four twolayermetal fab lines in Colorado Springs and Rousset (France). This is the same memory process Atmel uses for its E2PROM and flash devices, and for its 8051 chips with integrated flash. The 1200 measure about 24mm2 overall, and as the die photo in Figure 2 shows, the chip is nearly all logic. Memory processes typically don’t produce very pact (or fast) logic, but most AVR chips will be dominated by memory and peripherals, and clock speeds aren’t very high. Figure 2. The 90S1200 measures about 180。 mm in Atmel’s twolayermetal flashmemory process. For Once, RISC Techniques Improve Code Density It’s sometimes hard to get excited about 8bit processors, yet Atmel’s AVR design is as different from others in its class as the first RISC machine was from big systems more than a decade ago. With its large register file and orthogonal instruction set, AVR is far more modern than its petitors. Atmel’s new CPU will be particularly appealing to programmers moving down the microprocessor food chain from 32bit or 16bit chips and who are accustomed to flexible register sets. For programmers moving up from, say, the 8051, AVR will be a real eyeopener. For example, the 8051, 6805, and PIC all make do with a single accumulator。 the 68HC11 and ’HC12 have just two. This makes AVR easier to program at the assembly level and easier to optimize with a piler. The big register set reduces dependence on memory, which improves speed and shrinks datastorage requirements. Counterintuitively, AVR’s RISClike instruction set also helps improve its code density over that of other 8bitters, according to Atmel. Its CPI (pare immediate) instruction avoids the relatively awkward construct of loading, su
范文總結(jié)相關(guān)推薦
鄂ICP備17016276號(hào)-1