【文章內(nèi)容簡介】 or * CPU clock: * Operating voltage: * 2Kword working SRAM * 32Kword flash memory * Softwarebased audio processing * Crystal Resonator * Standby mode (Clock Stop mode) for power savings, A @ VDD = * Two 16bit timers/counters * Two 10bit DAC outputs * 32 general I/Os (bit programmable) 10 * 14 INT sources with two priority levels * Key wakeup function (IOA0 7) * Approx. 190 sec speech @ * PLL feature for system clock * 32768Hz Real Time Clock (RTC) * Eight channels 10bit AD converter ADC external top reference voltage * Builtin microphone amplifier and AGC function * UART receiver and transmitter (full duplex) * Low voltage reset and low voltage detection * Security function to protect code to be read and written. 3 APPLICATION FIELD * Voice recognition products * Intelligent interactive talking toys * Advanced educational toys * Kids learning products * Kids storybook * General speech synthesizer * Long duration audio products * Recording / playback products 4 FUNCTIONAL DESCRIPTIONS CPU The SPCE061A is equipped with a 16bit μ’ nSP(TM), the newest 16bit microprocessor by Sunplus and pronounced as micronSP. Eight registers are involved in μ’ nSP(TM): R1 R4 (Generalpurpose registers), PC (Program Counter), SP (Stack Pointer), Base Pointer (BP) and SR (Segment Register). The interrupts include three FIQs (Fast Interrupt Request) and eight IRQs (Interrupt Request), plus one softwareinterrupt, BREAK. 11 Moreover, a high performance hardware multiplier with the capability of FIR filter is also built in to reduce the software multiplication loading. Memory SRAM The amount of SRAM is 2Kword (including Stack), ranged from 0000 through 07FF with access speed of two CPU clock cycles. Flash memory Flash memory (008000 00FFFF) is a highspeed memory with access speed of two CPU clock cycles. FLASH erase and program functions must be used in IDE tools. PLL, Clock, Power Mode PLL (Phase Lock Loop) The purpose of PLL is to provide a base frequency (32768Hz) and to pump the frequency from to for system clock (Fosc). The default PLL frequency is . (1)System clock Basically,the system clock is provided by PLL and programmed by the Port_SystemClock (W) to determine the frequency of clock for system. The default system clock Fosc = and CPU clock is Fosc/8 if not specified. The initial CPU clock is Fosc/8 after system wakes up and to be adjusted to desired CPU clock by programming the Port_SystemClock (W).This avoids Flash ROM reading failure when system wakes up. (2)32768Hz RTC The Real Time Clock (RTC) is normally used in watch, clock or other time related products. A 2HzRTC (1/2 second) function is loaded in SPCE061A. The RTC counts the timing as well as to wake CPU up whenever RTC occurs. Since the RTC is generated each seconds, time can be traced by the numbers of RTC addition,SPCE061A supports 32768Hz oscillator in normal mode and autopowersaving normal mode, 32768Hz OSC always runs at the highest power autopowersaving mode, however, it runs in normal mode for the first 12 seconds and changes back to powersaving mode automatically to save powers. Standby Mode The SPCE061A also offers a standby mode for low power application needs. To enter standby mode, the desired key wakeup port (IOA [7:0]) must be configured to input first. And read the Port_IOA_Latch(R) to latch the IOA state before entering the standby mode. Also remember to enable the corresponding interrupt source(s) for wakeup. After that, stop the CPU clock by writing the STOP CLOCK Register (b0b2 of Port_SystemClock (W)) to enter standby mode. In such mode, SRAM and I/Os remain in the previous states till CPU being awoken. The wakeup sources in SPCE061A include Port IOA7 0 and IRQ1 IRQ6. After SPCE061A is awoken, the CPU will continue to execute the program. Programmer can also enable or disable the 32768Hz OSC when CPU is in standby mode. Low Voltage Detection and Low Voltage Reset Low voltage detection (LVD) There are two LVD levels to be selected: , and . These levels can be programmed via Port_LVD_Ctrl (W). As an example,