【文章內(nèi)容簡介】 ing the vertical sync pulse at pin 3 of the LM1881. If the default vertical sync period ends before the end of the input vertical sync period, then the falling edge of the vertical sync (positive pulse at the ―D‖ flipflop) will clock the high output from the parator with V1 as a reference input. This will retrigger the oscillator, generating a second vertical sync output pulse. The ―Vertical Default Sync Delay Time vs RSET‖ graph shows the relationship between the RSET value and the delay time from the start of the vertical sync period before the default vertical sync pulse is generated. Using the NTSC example again the smallest resistor for RSET is 500 k?. The vertical default time delay is about 50 181。s, much longer than the 30 181。s serration pulse spacing. A mon question is how can one calculate the required RSET with a video timing standard that has no serration pulses during the vertical blanking. If the default vertical sync is to be used this is a very easy task. Use the ―Vertical Default Sync Delay Time vsRSET‖ graph to select the necessary RSET to give the desired delay time for the vertical sync output signal. If a second pulse is undesirable, then check the ―Vertical Pulse Width vs RSET‖ graph to make sure the vertical output pulse will extend beyond the end of the input vertical sync period. In most systems the end of the vertical sync period may be very accurate. In this case the preferred design may be to start the vertical sync pulse at the end of the vertical sync period, similar to starting the vertical sync pulse after the first serration pulse. A VGA standard is to be used as an example to show how this is done. In this standard a horizontal line is 32 181。s long. The vertical sync period is two horizontal lines long, or 64 181。s. The vertical default sync delay time must be longer than the vertical sync period of 64 181。s. In this case RSET must be larger than 680 must still be small enough for the output of the integrator to reach V1 before the end of the vertical period of the input pulse. The first graph can be used to confirm that RSET is small enough for the integrator. Instead of using the vertical serration pulse separation, use the actual pulse width of the vertical sync period, or 64 181。s in this graph is linear, meaning that a value as large as M? can be used for RSET (twice the value as the maximum at 30 181。s). Due to leakage currents it is advisable to keep the value of RSET under M?. In this example a value of M? is selected, well above the minimum of 680 k?. With this value for RSET the pulse width of the vertical sync output pulse of the LM1881 is about 340 181。s. ODD/EVEN FIELD PULSE An unusual feature of LM1881 is an output level from Pin 7 that identifies the video field present at the input to the LM1881. This can be useful in frame memory storage applications or in extracting test signals that occur in alternate fields. For a posite video signal that is interlaced, one of the two fields that make up each video frame or picture must have a half horizontal scan line period at the end of the vertical scan— ., at the bottom of the picture. This is called the ―odd field‖ or ―even field‖. The ―even field‖ or ―field 2‖ has a plete horizontal scan line at the end of the field. An odd field starts on the leading edge of the first equalizing pulse, whereas the even field starts on the leading edge of the second equalizing pulse of the vertical retrace interval. Figure 1(a) shows the end of the even field and the start of the odd field. To detect the odd/even fields the LM1881 again integrates the posite sync waveform (Figure 2). A capacitor is charged during the period between sync pulses and discharged when the sync pulse is present. The period between normal horizontal sync pulses is enough to allow the capacitor voltage to reach a threshold level of a parator that clears a flipflop which is also being clocked by the sync waveform. When the vertical interval is reached, the shorter integration time between equalizing pulses prevents this threshold from being reached and the Q output of the flipflop is toggled with each equalizing pulse. Since the half line period at the end of the odd field will have the same effect as an equalizing pulse period, the Q output will have a different polarity on successive fields. Thus by paring the Q polarity with the vertical output pulse, an odd/even field index is generated. Pin 7 remains low during the even field and high during the odd field. BURST/BACKPORCH OUTPUT PULSE In a posite video signal, the chroma burst is located on the backporch of the horizontal blanking period. This period, approximately 181。s long, is also the black level reference for the subsequent video scan line. The LM1881 generates a pulse at Pin 5 that can be used either to retrieve the chroma burst from the posite video signal (thus providing a subcarrier synchronizing signal) or as a clamp for the DC restoration of the video waveform. This output is obtained simply by charging an internal capacitor starting on the trailing edge of the horizontal sync pulses. Simultaneously the output of Pin 5 is pulled low and held until the capacitor charge circuit times out— 4 181。s later. A shorter output burst gate pulse can be derived by differentiating the burst output using a series CR work. This may