【文章內(nèi)容簡(jiǎn)介】 沒(méi)有最低時(shí)鐘頻率的要求， Altera 公司建議您設(shè)計(jì)的系統(tǒng)時(shí)鐘頻率至少四倍 JTAG 時(shí)鐘頻率，以確保芯片上的儀器（ OCI）核心功能正常。 下載并執(zhí)行軟件 下載軟件是指為可執(zhí)行代碼和數(shù)據(jù)下載到的能力通過(guò) JTAG 連接處理器的 內(nèi)存。下載軟件后， JTAG 調(diào)試模塊可以退出調(diào)試模式并將執(zhí)行權(quán)轉(zhuǎn)由內(nèi)存可執(zhí)行代碼的開(kāi)始。 軟件斷點(diǎn) 軟件斷點(diǎn)讓你駐留在 RAM 中的指令上設(shè)置斷點(diǎn)。該軟件斷點(diǎn)機(jī)制寫入斷點(diǎn)指令轉(zhuǎn)換成可執(zhí)行代碼存儲(chǔ)在 RAM 中。當(dāng)處理器執(zhí)行的指令休息，控制轉(zhuǎn)移到 JTAG 調(diào)試模塊。 硬件斷點(diǎn) 硬件斷點(diǎn)允許你對(duì)居住在指令上設(shè)置斷點(diǎn)非易失性存儲(chǔ)器，如閃存。硬件斷點(diǎn)機(jī)制連續(xù)監(jiān)視處理器的當(dāng)前指令的地址。如果該指令的地址硬件斷點(diǎn)地址匹配時(shí)， JTAG 調(diào)試模塊需要控制處理器。 硬件斷點(diǎn)使用 JTAG 調(diào)試模塊的硬件實(shí)現(xiàn)觸發(fā)功能。 硬件觸發(fā) 硬件觸發(fā)器激 活基于對(duì)指令或條件調(diào)試操作 實(shí)時(shí)程序執(zhí)行過(guò)程中的數(shù)據(jù)總線。觸發(fā)器可以做多叫停處理器執(zhí)行。例如，觸發(fā)器可以被用來(lái)使跟蹤數(shù)據(jù)收集在實(shí)時(shí)處理器執(zhí)行。 目標(biāo)觸發(fā)器 JTAG 調(diào)試模塊提供了兩個(gè)級(jí)別的觸發(fā)功能，稱為目標(biāo)觸發(fā)器。目標(biāo)觸發(fā)器使能JTAG 調(diào)試模塊， B 事件上觸發(fā)而 A 事件不觸發(fā)轉(zhuǎn)化為， A 事件導(dǎo)致觸發(fā)動(dòng)作，使觸發(fā)器 B 事件觸發(fā)。 觸發(fā)值的范圍 JTAG 調(diào)試模塊可對(duì)數(shù)據(jù)或地址值的范圍上的數(shù)據(jù)觸發(fā)總線。這種機(jī)制使用兩個(gè)硬件觸發(fā)，共同創(chuàng)造一個(gè)觸發(fā)條件激活的范圍在規(guī)定范圍內(nèi)的值。 跟蹤捕獲 跟蹤捕獲是指能夠記錄的指令， 由指令執(zhí)行的因?yàn)樗趯?shí)時(shí)執(zhí)行代碼的處理器。 JTAG 調(diào)試模塊提供以下跟蹤功能： ■捕獲執(zhí)行跟蹤（指令總線周期）。 ■捕獲數(shù)據(jù)跟蹤（數(shù)據(jù)總線周期）。 ■對(duì)于每個(gè)數(shù)據(jù)總線周期，捕獲地址，數(shù)據(jù)，或兩者兼而有之。 ■啟動(dòng)和停止捕獲跟蹤，實(shí)時(shí)，基于觸發(fā)器。 ■手動(dòng)啟動(dòng)和主機(jī)控制下停止跟蹤。 ■可選擇停止捕獲跟蹤時(shí)，跟蹤緩沖區(qū)已滿，留下處理器執(zhí)行。 ■在片上內(nèi)存緩沖區(qū)的 JTAG 調(diào)試模塊中存儲(chǔ)跟蹤數(shù)據(jù)。 （此內(nèi)存是只能通過(guò) JTAG連接。 ） ■存儲(chǔ)跟蹤數(shù)據(jù)在片調(diào)試探頭較大的緩沖區(qū)。 某些跟蹤功能需要額外的許可證或調(diào)試工具 來(lái)自第三方調(diào)試提供商。例如，一個(gè)片上跟蹤緩沖器的一個(gè)標(biāo)準(zhǔn)功能 Nios II 處理器，而是采用了片上跟蹤緩沖器需要額外的調(diào)試軟件和 MIPS 科技或勞特巴赫有限公司提供的硬件。 有關(guān)詳細(xì)信息，請(qǐng)搜索關(guān)于 MIPS 科技網(wǎng)站（ ）和勞特巴赫有限公司網(wǎng)站（ ）的“ Nios II”。 執(zhí)行與數(shù)據(jù)跟蹤 JTAG 調(diào)試模塊支持跟蹤指令總線（執(zhí)行跟蹤）時(shí)，數(shù)據(jù)總線（數(shù)據(jù)跟蹤），或兩者同時(shí)進(jìn)行。執(zhí)行跟蹤記錄只有的指令地址執(zhí)行，使您能夠分析在內(nèi)存（即，在其中的函數(shù)）代碼執(zhí)行。數(shù)據(jù) 跟蹤與記錄相關(guān)的數(shù)據(jù)每個(gè)加載和存儲(chǔ)操作的數(shù)據(jù)總線上。 JTAG 調(diào)試模塊可以篩選數(shù)據(jù)總線跟蹤實(shí)時(shí)捕捉以下內(nèi)容： ■負(fù)載地址 ■存儲(chǔ)地址 ■雙方加載和存儲(chǔ)地址 ■負(fù)載數(shù)據(jù) ■加載地址和數(shù)據(jù) ■存儲(chǔ)地址和數(shù)據(jù) ■地址和數(shù)據(jù)的加載和存儲(chǔ) ■在觸發(fā)事件的數(shù)據(jù)總線單一樣本 跟蹤幀 幀是一個(gè)單位的內(nèi)存分配，收集跟蹤數(shù)據(jù)。然而，幀并不是一個(gè)絕對(duì)的衡量跟蹤標(biāo)準(zhǔn)。 為了跟上處理器執(zhí)行實(shí)時(shí)步伐，進(jìn)行優(yōu)化執(zhí)行跟蹤，只存儲(chǔ)選中的地址，如分支，電路，陷阱和中斷。這些地址，可以從主機(jī)端的調(diào)試軟件，可以由指令執(zhí)行跟蹤進(jìn)行重建指 定的精確。此外，執(zhí)行跟蹤數(shù)據(jù)以壓縮格式被存儲(chǔ)，使得一個(gè)幀代表以上的一個(gè)指令。如這些優(yōu)化的結(jié)果，實(shí)際開(kāi)始和結(jié)束點(diǎn)跟蹤收集在執(zhí)行過(guò)程中可能會(huì)從用戶指定的啟動(dòng)和結(jié)束略有不同。 數(shù)據(jù)跟蹤存儲(chǔ)要求 100％跟蹤緩沖區(qū)實(shí)時(shí)加載和存儲(chǔ)。當(dāng)存儲(chǔ)到跟蹤緩沖區(qū)，數(shù)據(jù)跟蹤幀的優(yōu)先級(jí)低于執(zhí)行跟蹤框架。因此，當(dāng)數(shù)據(jù)幀在實(shí)時(shí)存儲(chǔ)時(shí)，執(zhí)行和跟蹤數(shù)據(jù)都不能保證正好與每個(gè)同步等。 附件 2：外文原文（復(fù)印件） 2. Processor Architecture This chapter describes the hardware structure of the Nios174。 II processor, including a discussion of all the functional units of the Nios II architecture and the fundamentals of the Nios II processor hardware implementation. This chapter contains the following sections: ■ “ Processor Implementation” on page 2– 2 ■ “ Register File” on page 2– 3 ■ “ Arithmetic Logic Unit” on page 2– 4 ■ “ Reset and Debug Signals” on page 2– 8 ■ “ Exception and Interrupt Controllers” on page 2– 8 ■ “ Memory and I/O Organization” on page 2– 10 ■ “ JTAG Debug Module” on page 2– 17 The Nios II architecture describes an instruction set architecture (ISA). The ISA in turn necessitates a set of functional units that implement the instructions. A Nios II processor core is a hardware design that implements the Nios II instruction set and supports the functional units described in this document. The processor core does not include peripherals or the connection logic to the outside world. It includes only the circuits required to implement the Nios II architecture. The Nios II architecture defines the following functional units: ■ Register file ■ Arithmetic logic unit (ALU) ■ Interface to custom instruction logic ■ Exception controller ■ Internal or external interrupt controller ■ Instruction bus ■ Data bus ■ Memory management unit (MMU) ■ Memory protection unit (MPU) ■ Instruction and data cache memories ■ Tightlycoupled memory interfaces for instructions and data ■ JTAG debug module Processor Implementation The functional units of the Nios II architecture form the foundation for the Nios II instruction set. However, this does not indicate that any unit is implemented in hardware. The Nios II architecture describes an instruction set, not a particular hardware implementation. A functional unit can be implemented in hardware, emulated in software, or omitted entirely. A Nios II implementation is a set of design choices embodied by a particular Nios II processor core. All implementations support the instruction set defined in the Instruction Set Reference chapter of the Nios II Processor Reference Handbook. Each implementation achieves specific objectives, such as smaller core size or higher performance. This flexibility allows the Nios II architecture to adapt to different target applications. Implementation variables generally fit one of three tradeoff patterns: more or less of a feature。 inclusion or exclusion of a feature。 hardware implementation or software emulation of a feature. An example of each tradeoff follows: ■ More or less of a feature— For example, to finetune performance, you can increase or decrease the amount of instruction cache memory. A larger cache increases execution speed of large programs, while a smaller cache conserves onchip memory resources. ■ Inclusion or exclusion of a feature— For example, to reduce cost, you can choose to omit the JTAG debug module. This decision conserves onchip logic and memory resources, but it eliminates the ability to use a software debugger to debug applications. ■ Hardware implementation or software emulation— For example, in control applications that rarely perform plex arithmetic, you can choose for the division instruction to be emulated in software. Removing the divide hardware conserves onchip resources but increases the execution time of division operations. For information about which Nios II cores supports what features, refer to the Nios II Core Implementation Details chapter of the Nios II Processor Reference Handbook. For plete details about userselectable parameters for the Nios II processor, refer to the Instantiating the Nios II Processor chapter of the Nios II Processor Reference Handbook. Register File The Nios II architecture supports a flat register file, consisting of thirtytwo 32bit generalpurpose integer registers, and up to thirtytwo 32bit control registers. The architecture supports supervisor and user modes that allow system code to protect the control registers from errant a