【正文】 ( But u can still test the current chip using Low supply voltage, or High temperature or SS corner part that decrease hold time violation)what i meant was , when u have hold time violation , u dont need to throw away chip and wait for 3 months for fixed chip to e back. in the meanwhile , by playing with voltage and temperature , u can do other functional tests on the chip . since normally hold time simulation are done at FF corner , high voltage, low temperature which is the pessimistic case for hold time , by decreasing voltage , using high temperature, and a SS corner chip , we may be lucky enough to find a part that works , to do other functional tests to catch any other bugs before next tapeout.下面這個比較詳細：Sunil Budumuru：Pls. make a note that HOLD violations are dangerous than SETUP. To keep it simple way, SETUP timing depends on the frequency of operation. But HOLD time is not. Let us see the equations here. T = Frequency of operation (can be variable) Tcq = Flop clock to Flop output delay (fixed/constant) Tb = Delay od the binational logic between the Flops (can be variable) Tsetup = Setup time of a Flop (fixed/constant) Thold = Hold time of a Flop (fixed/constant) Tskew = Delay between clock edges of two adjacent flops (delay offered by clock path) (can be variable) For SETUP, T = Tcq + Tb + Tsetup Tskew If you have setup time means u r violating the above rule. some how the equation bees T Tcq + Tb + Tsetup Tskew Now let us consider two cases. Case1: During the Design development phase itself. Now, you have three variables (T, Tb, Tskew.) to avoid the setup violation. T : Reduce the frequency such that u saticify T = Tcq + Tb + Tsetup Tskew. But do u think it is the correct solution. Obviously, NO. This is because we have other options to avoid setup violations right. Tb : If you reduce the binational delay (between the Flops of violated path) such a way that T Tcq + Tb + Tsetup Tskew will bee T = Tcq + Tb + Tsetup Tskew. So, the SETUP violation is avoided. How do u reduce the binational delay??? Try different logic structure without effecting the functionality. or try to reduce the more fanout nets within the logic. Or upsize or downsize the cells. If it worked out thats fine. Tskew: If u increase the skew, u can change T Tcq + Tb + Tsetup Tskew to T = Tcq + Tb + Tsetup Tskew. How to increase the Tskew? Just keep buffers in the clock path. But be sure doesnt effect the HOLD timing. Case2: After the CHIP is manufatured and is in your hand. In this case, one cannot access the Tb and Tskew. Only the variable that can handle is T. So, Just reduce the frequency (T) such that the violated equation, T Tcq + Tb + Tsetup Tskew bees violation free equation T = Tcq + Tb + Tsetup Tskew. So, if u have setup violations on a manufatured chip, u can make it work by reducing the frequency. For HOLD, Thold + Tskew = Tcq + Tb If you have setup time means u r violating the above rule. some how the equation bees Thold + Tskew Tcq + Tb and ur aim is to make Thold + Tskew = Tcq + Tb Now let us consider two cases. Case1: During the Design development phase itself. You have two variables in hand (Tb, Tskew) to avoid HOLD violations. Tb: Increase the Tb by adding buffers in the data path. Thus u can change the situation from Thold + Tskew Tcq + Tb to Thold + Tskew = Tcq + Tb. But this might effect the SETUP time as you are increasing the delay of binational path. So this may not be the perfect solution always. Tskew : Reduce the clock skew so that you will land on Thold + Tskew = Tcq + Tb. To reduce the clock skew, the best solution is to take the help of your PNR engineer. Case2: After the CHIP is manufatured and is in your hand. Do you see any variables that will fix the hold violations after manufaturing?????!!!!!! NO right. So, its time to DUMP the chip as we dont deliver malfunctioning chips to the customers. So becareful with the HOLD violations. Note: One can get those equations if u put the those scenarios on a paper and develop the timing diagrams. Hope I39。 靜態(tài)時序分析工具以約束作為判斷時序是否滿足設(shè)計要求的標準，因此要求設(shè)計者正確輸入約束，以便靜態(tài)時序分析工具輸出正確的時序分析報告。時鐘的最小周期為：TCLK = TCKO +TLOGIC +TNET +TSETUP －TCLK_SKEWTCLK_SKEW =TCD2 －TCD1其中TCKO為時鐘輸出時間，TLOGIC為同步元件之間的組合邏輯延遲，TNET為網(wǎng)線延遲，TSETUP為同步元件的建立時間，TCLK_SKEW為時鐘信號延遲的差別。 公式2將公式1代入公式2：Tarrival+Tinput+TsetupTclk_skew=Tclk, 而Tclk_skew滿足時序關(guān)系后為負，所以TARRIVAL +TINPUT+TSETUP TCLKXilinx把上述約束統(tǒng)稱為：OFFSET約束（偏移約束），一共有4個相關(guān)約束屬性：OFFSET_IN_BEFORE、OFFSET_IN_AFTER、OFFSET_OUT_BEFORE和OFFSET_OUT_AFTER。BEFORE CLK約束，也可以直接對芯片內(nèi)部的輸出邏輯直接進行約束，NET DATA_OUT OFFET=OUT 它與Xilinx的時序定義中，有一個概念叫Tcko是同一個概念?；氐紸ltera的時序概念，Altera的tsu定義如下：tsu = Data Delay – Clock Delay + Micro tsuClock Hold Time tH時鐘保持時間是只能保證有效時鐘沿正確采用的數(shù)據(jù)和使能信號的最小穩(wěn)定時間。 BEFORE CLK其中TDELAY為要求的芯片內(nèi)部輸入延遲，其最大值與輸入數(shù)據(jù)到達時間TARRIVAL的關(guān)系如帖6所述:TDELAY_MAX + TARRIVAL = TPERIOD,所以TDELAY TPERIOD TARRIVAL = 20 14 =6 ns.輸出偏移約束例：設(shè)時鐘周期為20ns，后級輸入邏輯延時TINPUT為4ns、建立時間TSETUP為1ns，中間邏輯TLOGIC的延時為10ns，那么TSTABLE=15ns，于是可以在數(shù)據(jù)輸入引腳附加NET DATA_OUT OFFET=OUT比較難以確定的是TINPUT和TOUTPUT兩個時間量。 【周期（PERIOD）的含義】周期的含義是時序中最簡單也是最重要的含義，其它很多時序概念會因為軟件商不同略有差異，而周期的概念確是最通用的，周期的概念是FPGA/ASIC時序定義的基礎(chǔ)概念。為了解決大家的疑難，我們將逐一討論這些問題。 它們的走線時延的關(guān)系如下：同一個LAB中（最快） 同列或者同行 不同行且不同列。 這個問題是在設(shè)計中必須考慮的問題，只有弄清了這個問題才能保證所設(shè)計的組合邏輯的延時是否滿足了要求。同樣的可以解釋負的hold t