基于fpga的spwm波形發(fā)生器(專(zhuān)業(yè)版)
【正文】 ELSE Y =39。 addr_t64= q64_v。 END add_sin。 end if。 entity fenpin IS port(clk:in std_logic。在正弦波半個(gè)周期內(nèi) , 正負(fù)脈沖的面積總和與正弦波的面積相等。 Direct Digital Frenqency Synthsis 引言 新型電力電子器件和高性能微處理器的出現(xiàn)和發(fā)展 , 使得 PWM技術(shù)已成為電力電子技術(shù)中非常重要的組成部分 , 多種方法可以產(chǎn) 生 SPWM脈寬調(diào)制波。 第 2 頁(yè) 關(guān)鍵詞 ： FPGA； SPWM；功能時(shí)序仿真；直接數(shù)字頻率合成 Nowadays, DCAC inverters with Sinusoid Pulse Width Modulation (SPWM) techniques are widely used in electric power, postal, telemunications , aerospace and other fields. The SPWM controllers, which regulate the voltage and frequency by adjusting the SPWM signals, are the core of the inverters. The performance of the controller, directly determines the performance of the inverter. A design method of FPGAbased SPWM inverter controller is proposed in this thesis. Detailed design of this controller is carried out on Altera QuartusⅡ software, with the toptodown approach. The SPWM inverter controller is prised of seven functional modules, which are easy to transplant and upgrade. Therefore the whole control system can be upgraded easily. After the RTL level design is pleted, simulation is made on every module Key words: Field Programmable Gate Arrays 。圖 1 給出了雙極式 SPWM 的原理示意圖。 use 。139。 use 。
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