【正文】 . The inputs are the clock and reset signals. The values of major busses and important control signals are copied and output from the top level so that they are available for easy display in simulations. Signals that are not outputs at the top level will occasionally not exist due to the pilers logic optimizations during synthesis. Top Level Structural Model for MIPS Processor Core LIBRARY IEEE。Register 2 = value of memory at address B LW $3, C 。 ALU_result_out, read_data_1_out, read_data_2_out, write_data_out, Instruction_out OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 PC_out OUT STD_LOGIC_VECTOR( 9 DOWNTO 0 )。 RegWrite, MemtoReg IN STD_LOGIC。 MemtoReg OUT STD_LOGIC。 COMPONENT Execute PORT( Read_data_1 IN STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 Add_Result OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 )。 Clock,reset IN STD_LOGIC )。 SIGNAL read_data STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 SIGNAL MemRead STD_LOGIC。139。 ID Idecode PORT MAP ( read_data_1 = read_data_1, read_data_2 = read_data_2, Instruction = Instruction, read_data = read_data, ALU_result = ALU_result, RegWrite = RegWrite, MemtoReg = MemtoReg, RegDst = RegDst, Sign_extend = Sign_extend, clock = clock, reset = reset )。 USE 。 Branch OUT STD_LOGIC。039。039。 RegWrite = R_format OR Lw。 USE 。 SIGNAL Branch IN STD_LOGIC。 Instructions always start on a word address not byte PC(1 DOWNTO 0) = 00。 ) AND ( Zero = 39。139。 USE 。 MemtoReg IN STD_LOGIC。 SIGNAL write_data STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 write_register_address_1 = Instruction( 15 DOWNTO 11 )。 Mux to bypass data memory for Rformat instructions write_data = ALU_result( 31 DOWNTO 0 ) WHEN ( MemtoReg = 39。 PROCESS BEGIN WAIT UNTIL clock39。t write to register 0 ELSIF RegWrite = 39。 USE 。 Zero OUT STD_LOGIC。 SIGNAL Branch_Add STD_LOGIC_VECTOR( 8 DOWNTO 0 )。 ALU_ctl( 2 ) = ( Function_opcode( 1 ) AND ALUOp( 1 )) OR ALUOp( 0 )。 Adder to pute Branch Address Branch_Add = PC_plus_4( 9 DOWNTO 2 ) + Sign_extend( 7 DOWNTO 0 ) 。 ALU performs ALUresult = A_input B_input WHEN 110 = ALU_output_mux = Ainput Binput。 USE 。 外文翻譯（原文） 20 clock, reset IN STD_LOGIC )。s execution and correct operation. Return to the simulator and run the simulation again. Examine the ALU output in the timing diagram window. Zoom in on the ALU output during execution of the add instruction and see what happens when it changes values. Explain exactly what is happening at this point. Hint: Real hardware has timing delays. 2. Repile the MIPS model using the file, which generates video output. Downlo。 ARCHITECTURE behavior OF dmemory IS SIGNAL write_clock STD_LOGIC。 LIBRARY altera_mf。 WHEN OTHERS = ALU_output_mux = X00000000 。 PROCESS ( ALU_ctl, Ainput, Binput ) BEGIN Select ALU operation CASE ALU_ctl IS ALU performs ALUresult = A_input AND B_input WHEN 000 = ALU_output_mux = Ainput AND Binput。139。 BEGIN Ainput = Read_data_1。 Add_Result OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 )。 ENTITY Execute IS PORT( Read_data_1 IN STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 AND write_register_address = 0 THEN register_array( CONV_INTEGER( write_register_address)) = write_data。139。 ) ELSE read_data。 Instruction_immediate_value = Instruction( 15 DOWNTO 0 )。 外文翻譯（原文） 16 SIGNAL read_register_2_address STD_LOGIC_VECTOR( 4 DOWNTO 0 )。 Sign_extend OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 ENTITY Idecode IS PORT( read_data_1 OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 ELSE PC( 9 DOWNTO 2 ) = Next_PC。 ) ) ELSE PC_plus_4( 9 DOWNTO 2 )。 PC_plus_4_out = PC_plus_4。 SIGNAL PC_out OUT STD_LOGIC_VECTOR( 9 DOWNTO 0 )。 USE 。 MemWrite = Sw。139。139。 clock, reset IN STD_LOGIC )。 RegDst OUT STD_LOGIC。 EXE Execute PORT MAP ( Read_data_1 = read_data_1, Read_data_2 = read_data_2, Sign_extend = Sign_extend, Function_opcode = Instruction( 5 DOWNTO 0 ), ALUOp = ALUop, ALUSrc = ALUSrc, Zero = Zero, ALU_Result = ALU_Result, Add_Result = Add_Result, PC_plus_4 = PC_plus_4, 外文翻譯（原文） 10 Clock = clock, Reset = reset )。 Branch_out = Branch。 SIGNAL Instruction STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 SIGNAL Branch STD_LOGIC。 declare signals used to connect VHDL ponents SIGNAL PC_plus_4 STD_LOGIC_VECTOR( 9 DOWNTO 0 )。 clock, reset IN STD_LOGIC )。 Sign_Extend IN STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 MemRead OUT STD_LOGIC。 Sign_extend OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 END COMPONENT。 END TOP_SPIM。Register 4 = B + C SW $4, A 。Register 3 = value of memory at address C ADD $4, $2, $3 。 Branch_out, Zero_out, Memwrite_out, Regwrite_out OUT STD_LOGIC )。 clock,reset IN STD_LOGIC )。 RegDst IN STD_LOGIC。 RegWrite OUT STD_LOGIC。 Read_data_2 IN STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 PC_plus_4 IN STD_LOGIC_VECTOR( 9 DOWNTO 0 )。 END COMPONENT。 SIGNAL ALUSrc STD_LOGIC。 SIGNAL ALUop STD_LOGIC_VECTOR( 1 DOWNTO 0 )。 ELSE ALU_result。 CTL control PORT MAP ( Opcode = Instruction( 31 DOWNTO 26 ), RegDst = RegDst, ALUSrc = ALUSrc, MemtoReg = MemtoReg, RegWrite = RegWrite, MemRead = MemRead, MemWrite = MemWrite, Branch = Branch, ALUop = ALUop, clock = clock, reset = reset )。 ENTITY control IS PORT( Opcode IN STD_LOGIC_VECTOR( 5 DOWNTO 0 )。 ALUop OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 )。 Lw = 39。 Beq = 39。 MemRead = Lw。 USE 。 SIGNAL Zero IN STD_LOGIC。 copy output signals allows read inside module PC_out = PC。139。 THEN PC = 0000000000 。 USE 。 RegDst IN STD_LOGIC。 SIGNAL read_register_1_address STD_LOGIC_VECTOR( 4 DOWNTO 0 )。 write_register_address_0 = Instruction( 20 DOWNTO 16 )。039。EVENT AND clock = 39。139。 USE 。 ALU_Result OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 SIGNAL ALU_ctl STD_LOGIC_VECTOR( 2 DOWNTO 0 )。 Generate Zero Flag Zero = 39。 Add_result = Branch_Add( 7 DOWNTO 0 )。 外文翻譯（原文） 19 ALU performs SLT WHEN 111 = ALU_output_mux = Ainput Binput 。 USE 。 END dmemo