【正文】 ted to 256 locations of 32bit memory. Data memory is implemented using the Altsyncram megafunction. Memory write cycle timing is critical in any design. The Altsyncram function requires an internal address register with a clock. In this design, the falling clock edge is used to load the data memories internal address register. The rising clock edge starts the next instruction. Two M4K RAM blocks are used for data memory. Two M4K RAM blocks are also used for the 32bit instruction memory. Figure Block Diagram of MIPS Data Memory Unit Dmemory module (implements the data memory for the MIPS puter) LIBRARY IEEE。 write_data IN STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 END behavior。 Load memory address amp。 ENTITY dmemory IS PORT( read_data OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 END PROCESS。 ALU performs ALUresult = A_input + B_input WHEN 010 = ALU_output_mux = Ainput + Binput。039。039。 clock, reset IN STD_LOGIC )。 Sign_extend IN STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 END PROCESS。139。 Instruction_immediate_value WHEN Instruction_immediate_value(15) = 39。 Read Register 2 Operation read_data_2 = register_array( CONV_INTEGER( read_register_2_address) )。 SIGNAL write_register_address_0 STD_LOGIC_VECTOR( 4 DOWNTO 0 )。 END Idecode。 Instruction IN STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 END PROCESS。EVENT ) AND ( clock = 39。 Adder to increment PC by 4 PC_plus_4( 9 DOWNTO 2 ) = PC( 9 DOWNTO 2 ) + 1。 END Ifetch。 USE 。 ALUOp( 1 ) = R_format。039。039。 外文翻譯（原文） 11 ARCHITECTURE behavior OF control IS SIGNAL R_format, Lw, Sw, Beq STD_LOGIC。 MemtoReg OUT STD_LOGIC。 END structure。 RegWrite_out = RegWrite。 ALU_result_out = ALU_result。 SIGNAL Regwrite STD_LOGIC。 SIGNAL read_data_2 STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 COMPONENT dmemory PORT( read_data OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 ALUOp IN STD_LOGIC_VECTOR( 1 DOWNTO 0 )。 Branch OUT STD_LOGIC。 END COMPONENT。 read_data_2 OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 PC_plus_4_out OUT STD_LOGIC_VECTOR( 9 DOWNTO 0 )。 USE 。19952020 courtesy of Michael Davidson, Florida State University, The MIPS Instruction Set and Processor The MIPS is an example of a modern reduced instruction set puter (RISC) developed in the 1980s. The MIPS instruction set is used by NEC, Nintendo, Motorola, Sony, and licensed for use by numerous other semiconductor manufacturers. It has fixedlength 32bit instructions and thirtytwo 32bit generalpurpose registers. Register 0 always contains the value 0. A memory word is 32 bits wide. As seen in Table , the MIPS has only three instruction formats. Only I format LOAD and STORE instructions reference memory operands. Rformat instructions such as ADD, AND, and OR perform operations only on data in the registers. They require two register operands, Rs and Rt. The result of the operation is 外文翻譯（原文） 2 stored in a third register, Rd. Rformat shift and function fields are used as an extended opcode field. Jformat instructions include the jump instructions. Table MIPS 32bit Instruction Formats LW is the mnemonic for the Load Word instruction and SW is the mnemonic for Store Word. The following MIPS assembly language program putes A = B + C. LW $2, B 。 Output important signals to pins for easy display in Simulator PC OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 )。 Zero IN STD_LOGIC。 ALU_result IN STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 ALUSrc OUT STD_LOGIC。 END COMPONENT。 ALU_Result OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 MemRead, Memwrite IN STD_LOGIC。 SIGNAL ALU_result STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 SIGNAL MemtoReg STD_LOGIC。 write_data_out = read_data WHEN MemtoReg = 39。 PC_plus_4_out = PC_plus_4, 外文翻譯（原文） 9 Add_result = Add_result, Branch = Branch, Zero = Zero, PC_out = PC, clock = clock, reset = reset )。 USE 。 MemWrite OUT STD_LOGIC。 WHEN Opcode = 000000 ELSE 39。 WHEN Opcode = 101011 ELSE 39。 MemtoReg = Lw。 The Instruction Fetch Stage The instruction fetch stage of the MIPS shown in Figure contains the instruction memory, the program counter, and the hardware to increment the program counter to pute the next instruction address. Figure Block Diagram of MIPS Fetch Unit 外文翻譯（原文） 12 Instruction memory is implemented using the Altsyncram megafunction. 256 by 32 bits of instruction memory is available. This requires two of the Cyclone chip‘s M4K RAM memory blocks. Since the Altsyncram memory requires an address register, the PC register is actually implemented inside the memory block. A copy of the PC external to the memory block is also saved for use in simulation displays. Ifetch module (provides the PC and instruction memory for the MIPS puter) LIBRARY IEEE。 SIGNAL Add_result IN STD_LOGIC_VECTOR( 7 DOWNTO 0 )。 BEGIN ROM for Instruction Memory data_memory altsyncram GENERIC MAP ( operation_mode = ROM, width_a = 32, widthad_a = 8, lpm_type = altsyncram, outdata_reg_a = UNREGISTERED, Reads in mif file for initial data memory values init_file = , intended_device_family = Cyclone) Fetch next instruction from memory using PC PORT MAP ( 外文翻譯（原文） 13 clock0 = clock, address_a = Mem_Addr, q_a = Instruction)。139。 IF reset = 39。 USE 。 RegWrite IN STD_LOGIC。 SIGNAL write_register_address STD_LOGIC_VECTOR( 4 DOWNTO 0 )。 read_register_2_address = Instruction( 20 DOWNTO 16 )。 ELSE write_register_address_0。 Instruction_immediate_value。 Write back to register don39。 USE 。 ALUSrc IN STD_LOGIC。 SIGNAL ALU_output_mux STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 ALU_ctl( 1 ) = ( NOT Function_opcode( 2 ) ) OR (NOT ALUOp( 1 ) )。 ALU_output_mux( 31 ) WHEN ALU_ctl = 111 ELSE ALU_output_mux( 31 DOWNTO 0 )。 ALU performs WHEN 101 = ALU_output_mux = X00000000 。 USE 。 MemRead, Memwrite IN STD_LOGIC。 MIPS data memory is initialized to the value specified in the file show