【正文】 nufacturing problems are foreseen and solutions to them are known, although not yet fully worked out。舉例來說，我可以使用真空二級(jí)管做為門電路，就象在 EDSAC 中一樣，或者在兩個(gè)柵格之間用帶控制信號(hào)的五級(jí)管，這被廣泛用于其他系統(tǒng)設(shè)計(jì)，這類的選擇一直在持續(xù)著直到邏輯門電路開始應(yīng)用。這些我認(rèn)為歸因與高級(jí)語言的起步和第一個(gè)操作系統(tǒng)的誕生。由此出現(xiàn)了我們所知道 7400 系列微機(jī)。微機(jī)的出現(xiàn)解決了這個(gè)局面。 7400 在 70 年代中期還不斷發(fā)展壯大，并且被寬帶局域網(wǎng)的先驅(qū)組織Cambridge Ring 所采用。該運(yùn)動(dòng)是由 Patterson 和 Ditzel 發(fā)表了一篇命名為精簡(jiǎn)指令計(jì)算機(jī)的情況論文而引起的。隨后，計(jì)算機(jī)設(shè)計(jì)者變的多些可理性少了一些藝術(shù)性。我們?nèi)孕枰粩嗵嵝盐覀冏约海何覀儜?yīng) 該嚴(yán)格的與先前的應(yīng)用在機(jī)器層面上保持兼容。當(dāng)致命的異常發(fā)生時(shí)， X86 引入的代碼是，經(jīng)過適當(dāng)?shù)拇鄹暮?，被轉(zhuǎn)化為它的內(nèi)部代碼并且被 RISC芯片處理。這打亂了傳統(tǒng)的在指令字長(zhǎng)和信息內(nèi)容的平衡，并且它改變了編譯器作者的原先的大綱。 AMD 已經(jīng)定義了一種 64 位的與 x86 更加兼容的指令集，并且他 們已經(jīng)取得了進(jìn)展。很多人認(rèn)為這才是 Intel 應(yīng)該做的。很難弄懂它所指的是什么。請(qǐng)參考特殊計(jì)算機(jī)體系構(gòu)造，第三版， 2020， P146， 1514，1578 IA64 指令集 很久以前， Intel 和 HewlettPackard 引進(jìn)了 IA64 指令集。有一個(gè)已經(jīng)取得了更大的成功，我所說的 i860(不是 i960,它們有一些不同 )。INTEL 8086 及其后裔都與 x86 密切相關(guān)。從某種意義上說，它推動(dòng)了線程的發(fā)展，在處理器中，同一時(shí)間有幾個(gè) 指令在不同的執(zhí)行階段稱為線程。在這兩種系統(tǒng)出現(xiàn)之前，人們大多滿足于基于電報(bào)交換機(jī)的本地局域網(wǎng)。這就是我在概要中提到的“通貨膨脹”在計(jì)算機(jī)工業(yè)中走上了歧途之說。他們可通過導(dǎo)線連接在一起，作成一個(gè)計(jì)算機(jī)或其他的東西。 綜上所述，晶體管開始代替正空管。 在最初的幾年， IEE（電子工程師協(xié)會(huì)）仍然由動(dòng)力工程占據(jù)主導(dǎo)地位。 Insulating layers in the most advanced chips are now approaching a thickness equal to that of 5 atoms. Beyond finding better insulating materials, and that cannot take us very far, there is nothing we can do about this. We may also expect to face problems with onchip wiring as wire cross sections get smaller. These will concern heat dissipation and atom migration. The above problems are very fundamental. If we cannot make wires and insulators, we cannot make a puter, whatever improvements there may be in the CMOS process or improvements in semiconductor materials. It is no good hoping that some new process or material might restart the merrygoround of the density of transistors doubling every eighteen months. I said above that there is a general expectation that shrinkage would continue by one means or another to 45 nm or even less. What I had in mi nd was that at some point further scaling of CMOS as we know it will bee impracticable, and the industry will need to look beyond it. Since 2020 the Roadmap has had a section entitled emerging research devices on nonconventional forms of CMOS and the like. Vigorous and opportunist exploitation of these possibilities will undoubtedly take us a useful way further along the road, but the Roadmap rightly distinguishes such progress from the traditional scaling of conventional CMOS that we have been used to. Advances in Memory Technology Unconventional CMOS could revolutionalize memory technology. Up to now, we have relied on DRAMs for main memory. Unfortunately, these are only increasing in speed marginally as shrinkage continues, whereas processor chips and their associated cache memory continue to double in speed every two years. The result is a growing gap in speed between the processor and the main memory. This is the memory gap and is a current source of anxiety. A breakthrough in memory technology, possibly using some form of unconventional CMOS, could lead to a major advance in overall performance on problems with large memory requirements, that is, problems which fail to fit into the cache. Perhaps this, rather than attaining marginally higher basis processor speed will be the ultimate role for nonconventional CMOS. Shortage of Electrons Although shortage of electrons has not so far appeared as an obvious limitation, in the long term it may bee so. Perhaps this is where the exploitation of nonconventional CMOS will lead us. However, some interesting work has been by Haroon Amed and his team working in the Cavendish the direct development of structures in which a single electron more or less makes the difference between a zero and a one. However very little progress has been made towards practical devices that could lead to the construction of a puter. Even with exceptionally good luck, many tens of years must inevitably elapse before a working puter based on single electron effects can be contemplated. 微機(jī)發(fā)展簡(jiǎn)史 IEEE 的論文 劍橋大學(xué)， 2020/2/5 莫里斯 威爾克斯 計(jì)算機(jī)實(shí)驗(yàn)室 劍橋大學(xué) 第一臺(tái)存儲(chǔ)程序的計(jì)算開始出現(xiàn)于 1950 前后，它就是 1949 年夏天在劍橋大學(xué)，我們創(chuàng)造的延遲存儲(chǔ)自動(dòng)電子計(jì)算機(jī)（ EDSAC）。 Progress in Computers Prestige Lecture delivered to IEE, Cambridge, on 5 February 2020 Maurice Wilkes Computer Laboratory University of Cambridge The first stored program puters began to work around 1950. The one we built in Cambridge, the EDSAC was first used in the summer of 1949. These early experimental puters were built by people like myself with varying backgrounds. We all had extensive experience in electronic engineering and were confident that that experience would stand us in good stead. This proved true, although we had some new things to learn. The most important of these was that transients must be treated correctly。 although it is not obvious, on the surface, a modern x86 processor chip contains hidden within it a RISCstyle processor with its own internal RISC coding. The ining x86 code is, after suitable massaging, converted into this internal code and handed over to the RISC processor where the critical execution is performed. In this summing up of the RISC movement, I rely heavily on the latest edition of Hennessy and Patterson’s books on puter design as my supporting authority。后來，被證明是正確的，盡管我們也要學(xué)習(xí)很多新東西。讓人有些憤怒的是，所有的 IEE 出版的論文都被期望以冗長(zhǎng)的早期研究的陳述開頭，無非是些在早期階段由于沒有太多經(jīng)驗(yàn)而遇到的困難之類的陳述。只能說他們鼓起勇氣接受了挑戰(zhàn)，盡管這個(gè)轉(zhuǎn)變并不會(huì)一帆風(fēng)順。他比大型機(jī)稍遜，但功能強(qiáng)大，并且更能讓人負(fù)擔(dān)的起。 7400系列的用戶能夠工作在邏輯門和開關(guān)級(jí)別并且芯片的集成 度可靠性比單獨(dú)晶體管高很多。 精簡(jiǎn)指令計(jì)算機(jī)的誕生 早期的計(jì)算機(jī)有簡(jiǎn)單的指令集，隨著時(shí)間的推移，商業(yè)用微機(jī)的設(shè)計(jì)者增加了另外的他們認(rèn)為可以微機(jī)性能的特性。我的意思是說利用目前存在的功能強(qiáng)大的計(jì)算機(jī)去模擬新的設(shè)計(jì)。 對(duì)于我們這些從事計(jì)算機(jī)學(xué)術(shù)研究的人， X86 的統(tǒng)治地位讓我們感到失望。直接應(yīng)用先前 x86 的實(shí)現(xiàn)方式對(duì)于滿足 RISC 處理器的持續(xù)增長(zhǎng)的速度要求，是不可能的。然而，人們普遍認(rèn)為 Intel 應(yīng)該與 x86 構(gòu)架保持兼容，可令人疑惑的是恰恰相反。因此，在任何情況下，作為常識(shí)和一般性的標(biāo)準(zhǔn)， Gordon Moore 在訪問劍橋最近開放的 Betty and Gordon Moore 圖書館時(shí)所反復(fù)強(qiáng)調(diào)