電氣專(zhuān)業(yè)畢業(yè)設(shè)計(jì)外文文獻(xiàn)與中文翻譯(完整版)
【正文】 采用相同預(yù)編程 OPP 的 DVFS 不同。盡管 ARM 組件的運(yùn)行速度可高達(dá) 600 MHz，但系統(tǒng)并不總是需要如此高的計(jì)算能力。s AVS / SmartReflex technology. In these descriptions, IVA refers to images, video and audio accelerator subsystem. Case I: devicedown mode mW. This is a TI OMAP can automatically wake up the minimum power mode. In this mode, the entire device in addition to wakeup outside the closed domain, and the wakeup frequency domain is less than 32 kHz. Close the regulator does not use (VDD1 = VDD2 = 0), autorefresh SDRAM, special start sequence when the wakeup call to restore the system state controller and the SDRAM. Case II: standby mode 7 mW. Devices in the state, only to wake up the domain, all other nonpower domain wakeup are in a lowpower state of preservation (VDD1 = VDD2 = V). All logic and memory will be retained. AVS closed. Case III: Audio Decoder 22 mW (excluding DPLL power and IO). Although the ARM in the 125 MHz frequency, but only from the DMA set multimedia card reader input data, and then enter hibernation. MP3 decoder IVA frame ( kHz, 128k bps stereo), and decoding the data sent to a buffer in SDRAM. Chip multichannel buffered serial port to send data to the audio codec for playback. On the system configuration is concerned, DSP39。s cool device in the frequency of 125 MHz need to volts, while the hot device in the frequency of only volts. Adaptive voltage scaling (AVS) technology uses the corresponding feedback loop supply voltage regulator to ensure that all devices running tasks in a specific frequency required Software can work for each OPP set up AVS hardware, and control algorithms through I2C bus to send mands to external voltage regulator in order to gradually reduce the output of the appropriate regulator, until just over the target processor frequency requirement. For example, developers can design a first to meet all of the voltage, frequency of 125 MHz at volts (in Figure 1 in the top of the V1). However, if the system using AVS technology to insert the hot device, then the feedback mechanism onchip ARM will automatically be reduced to volts of the voltage or lower (V2 in Figure 1 above). The first two active power management technology can minimize the operating voltage so that a certain part of the device in the desired speed. In contrast, the third method Dynamic power switching (DPS) to determine the device when it can plete the calculation of the current task, if no need, then allow the device to enter lowpower standby mode (Figure 2). For example, the processors are waiting for DMA transfer to plete the process will enter a lowpower state. Processor in a few microseconds after the wakeup call will be able to return to normal working condition.Figure 2 Dynamic power switching (DPS) in a given part of a device after the pletion of the task to enter the lowpower state Passive power management Although the DPS will allow multimedia systemonchip (SoC) as part of entering the lowpower state, but in some cases, we can have the entire device into the low power mode in the absence of the application to run automatically or through user request
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