現(xiàn)代cmos工藝基本流程課件(ppt79頁)(完整版)
【正文】 應(yīng)離子刻蝕 (RIE) –必須精確的從光刻膠得到多晶硅的形狀 27 Silicon Substrate P+ Silicon Epi Layer P P Well N Well Gate Oxide Poly Gate Electrode 除去光刻膠 28 Trench Oxide N Well P Well Cross Section Polysilicon 平面視圖 柵極 ? 完成柵極 29 Silicon Substrate P+ Silicon Epi Layer P P Well N Well Gate Oxide Poly Gate Electrode Poly Reoxidation 多晶硅氧化 ? 多晶硅氧化 –在多晶硅表面生長薄氧化層 –用于緩沖隔離多晶硅和后續(xù)步驟形成的Si3N4 30 Silicon Substrate P+ Silicon Epi Layer P P Well N Well Photoresist 光刻膠成形 ? 光刻膠成形 –用于控制 NMOS管的銜接注入 31 Silicon Substrate P+ Silicon Epi Layer P P Well N Well Photoresist Arsenic () Ions N Tip NMOS管銜接注入 ? NMOS管銜接注入 –低能量、淺深度、低摻雜的砷離子注入 –銜接注入用于削弱柵區(qū)的熱載流子效應(yīng) 32 Silicon Substrate P+ Silicon Epi Layer P P Well N Well N Tip 除去光刻膠 33 Silicon Substrate P+ Silicon Epi Layer P P Well N Well Photoresist N Tip 光刻膠成形 ? 光刻膠成形 –用于控制 PMOS管的銜接注入 34 Silicon Substrate P+ Silicon Epi Layer P P Well N Well Photoresist BF2 (+) Ions N Tip P Tip ? PMOS管銜接注入 –低能量、淺深度、低摻雜的 BF2+離子注入 –銜接注入用于削弱柵區(qū)的熱載流子效應(yīng) PMOS管銜接注入 35 Silicon Substrate P+ Silicon Epi Layer P P Well N Well N Tip P Tip 除去光刻膠 36 Silicon Substrate P+ Silicon Epi Layer P P Well N Well Silicon Nitride Thinner Here Thicker Here N Tip P Tip P Tip Si3N4淀積 ? Si3N4淀積 –厚度 120～ 180nm – CVD 37 Silicon Substrate P+ Silicon Epi Layer P P Well N Well Spacer Sidewall N Tip P Tip P Tip Si3N4刻蝕 ? Si3N4刻蝕 –水平表面的薄層 Si3N4被刻蝕，留下隔離側(cè)墻 –側(cè)墻精確定位晶體管源區(qū)和漏區(qū)的離子注入 – RIE 38 Silicon Substrate P+ Silicon Epi Layer P P Well N Well Photoresist N Tip P Tip 光刻膠成形 ? 光刻膠成形 –用于控制 NMOS管的源 /漏區(qū)注入 39 Silicon Substrate P+ Silicon Epi Layer P P Well N Well Photoresist Arsenic () Ions N+ Drain N+ Source P Tip NMOS管源 /漏注入 ? NMOS管源 /漏注入 –淺深度、重摻雜的砷離子注入，形成了重摻雜的源 /漏區(qū) –隔離側(cè)墻阻擋了柵區(qū)附近的注入 40 Silicon Substrate P+ Silicon Epi Layer P P Well N Well N+ Drain N+ Source P Tip 除去光刻膠 41 Silicon Substrate P+ Silicon Epi Layer P P Well N Well N+ Drain N+ Source Photoresist P Tip 光刻膠成形 ? 光刻膠成形 –用于控制 PMOS管的源 /漏區(qū)注入 42 Silicon Substrate P+ Silicon Epi Layer P P Well N Well BF2 (+) Ions Photoresist N+ Drain N+ Source P+ Source P+ Drain PMOS管源 /漏注入 ? PMOS管源 /漏注入 –淺深度、重摻雜的 BF2+離子注入，形成了重摻雜的源 /漏區(qū) –隔離側(cè)墻阻擋了柵區(qū)附近的注入 43 Silicon Substrate P+ Silicon Epi Layer P P Well N Well N+ Drain N+ Source P+ Source P+ Drain Lightly Doped “Tips” 除去光刻膠和退火 ? 除去光刻膠和退火 –用 RTP工藝，消除雜質(zhì)在源 /漏區(qū)的遷移 44 Trench Oxide Polysilicon Cross Section N Well P Well N+ Source/Drain P+ Source/Drai
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