外文翻譯--一個以“dsp算法和asic架構(gòu)”為導(dǎo)向的碩士課程(完整版)
【正文】 法和 ASIC架構(gòu)” 。因此，基本特征是： 量身定作指令集和； 以給定的應(yīng)用（即，一套算法）建拓?fù)浣Y(jié)構(gòu)構(gòu)成的執(zhí)行的單位調(diào)整。 在面向項目的設(shè)計工作中，學(xué)生的掌握了處理問題的訣竅是可以解決的理論和知識，他們演講已獲得理論知識。該種功能的調(diào)查，通常屬于下列類別： 從一觀察到的信號提取信息 消除 /減少不必要的信號元件 快捷及可靠的信號傳輸 /檢測 分析，修改和基準(zhǔn) DSP 算法在以便他們成為一個最佳的固定或可編程的目標(biāo)架構(gòu)。 一旦整體建筑結(jié)構(gòu)已決定，細(xì)化的過程是發(fā)起了那里的學(xué)生在詳細(xì)設(shè)計數(shù)據(jù)路徑。 在為了應(yīng)付這些系統(tǒng)和下列步驟，在設(shè) 計的軌跡（即，實際執(zhí)行），一套商業(yè)設(shè)計工具是必須的。最有力的表現(xiàn)是各種不同的碩士論文已先后進(jìn)行了例證，可不幸的是，寫在丹麥，也就是說，未來的目標(biāo)是讓我們的學(xué)生有更多的國際味道。一個小而有效率的評估電路板的基礎(chǔ)上， FLEX的 10k50 Altera的 FPGA的連接到一個 UART的為 PC的接口和雙 SRAM的提供數(shù)據(jù)和 programmemory ，可為每個項目組。最后，控制器的設(shè)計。 因此，課程包括： 各種算法和執(zhí)行單位（ EXU） 數(shù)據(jù)和控制路徑拓?fù)? 指令集和譯碼原則 配置多處理機(jī)系統(tǒng) 在多處理器系統(tǒng)的溝通 異質(zhì)性和可重構(gòu) DSP系統(tǒng) 軟 /硬體協(xié)同設(shè)計和驗證 用 VHDL編程，仿真和合成 FPGA的技術(shù)和設(shè)計工具 4．一個典型的項目軌跡 設(shè)計一個專門的實時 DSP 系統(tǒng)是由應(yīng)用水平發(fā)起的，即，首先學(xué)生要了解和描述的問題。項目工作有一個知道為什么態(tài)度和支持有關(guān)的講座。 經(jīng)過五年的不斷改進(jìn)，我們的碩士課程，現(xiàn)在已近非常成功了。 1．導(dǎo)言 在過去的二、三十年內(nèi)的數(shù)字信號處理一直朝向更精密和復(fù)雜的算法演變的最主要的原因是今天設(shè)計的非常強(qiáng)大，靈活和易于使用的通用（ GP ）的可編程數(shù)字信號處理器。s FLEXseries of FPGA. A small but efficient evaluation board, based on the FLEX 10K50 Altera FPGA connected to an UART for PC interfacing and dual SRAM providing data and programmemory, is available for each project group. 5. GENERAL EXPERIENCES Apart from minor modifications and updates, the Master programme is now running into its 6th year. Although the programme is quite intensive we found that it actually is possible during a two semester course to enable students to design operational FPGA prototype systems for plex DSP applications. The prerequisitions are a detailed knowledge of DSP theory and general digital circuit design. We are convinced that our success is due to the projectoriented education strategy. Working together in small groups, the students are highly motivated and prepared to spend some extra hours every day in order to achieve their project goals. Up til now, a variety of diffierent Master theses have been conducted, examples are available from [3] | some, unfortunately, are written in Danish, meaning that the next goal is to give our students a more international flavor. 附錄 B 一個以 “ DSP算法和 ASIC架構(gòu) ”為導(dǎo)向的碩士課程 在過去十年中數(shù)字信號處理（ DSP）已從一個只有少數(shù)專家認(rèn)知的術(shù)語，演變?yōu)橐粋€家喻戶曉的名詞。附錄 A A PROJECTORIENTED MASTER PROGRAMME IN DSP ALGORITHMS AND ASIC ARCHITECTURES Over the last decade Digital Signal Processing (DSP) has evolved from being a term known by only a few specialists, to a household term. The growth in DSP applied in ., consumer, medical, munications, working and puting devices has been spectacular. In fact, the digital signal processor market has grown 40% per year since 1988 and this figure is expected to continue over the next 10 years. At the same time the extreme improvement in hardware technologies has been paving the way for designing dedicated architectures for real time execution of still more plex DSP algorithms, continuously decreasing the power and silicon consumption required to perform certain functionalities. Consequently, we consider advanced DSP topics as being essential in the curriculum for a still growing number of
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