【正文】 PDC 定時器規(guī)格 功能 PDC 定時器 0 PDC 定時器 1 時鐘源 內部 時 鐘 : FCK/1 、 FCK/4 、FCK/16 、 FCK/64 、 FCK/256 、FCK/1024 外部時鐘 : TCLKA、 TCLKB 內部 時 鐘 : FCK/1 、 FCK/4 、FCK/16 、 FCK/64 、 FCK/256 、FCK/1024 外部時鐘 : TCLKA、 TCLKB IO 引腳 TIO0A, TIO0B, TIO0C TIO1A、 TIO1B、 TIO1C 定時通用寄存器 P_TMR0_TGRA、 P_TMR0_TGRB、 P_TMR0_TGRC P_TMR1_TGRA 、 P_TMR1_TGRB 、P_TMR1_TGRC 定時緩沖寄存器 P_TMR0_TBRA 、 P_TMR0_TBRB 、P_TMR0_TBRC P_TMR1_TBRA 、 P_TMR1_TBRB 、P_TMR1_TBRC 定時、計數寄存器 P_TMR0_TPR、 P_TMR0_TCNT P_TMR1_TPR、 P_TMR1_TCNT 捕獲采樣時鐘 內部時鐘 : FCK/ FCK/ FCK/FCK/8 內部時鐘 : FCK/ FCK/ FCK/FCK/8 計數邊沿 上升、下降、雙沿計數 上升、下降、雙沿計數 外文翻譯（譯文） 20 計數清除源 1 根據 P_TMR0_TGRA 、P_TMR0_TGRB、 P_TMR0_TGRC 捕獲輸入清除 2 根據 P_POS0_DectData偵測位置改變數據變化清除 3 根據 P_TMR0_TPR 比較匹配清除 1 根據 P_TMR1_TGRA 、 P_TMR1_TGRB、 P_TMR1_TGRC 捕 獲輸入清除 2 根據 P_POS1_DectData偵測位置改變數據變化清除 3 根據 P_TMR1_TPR 比較匹配清除 輸入捕獲功能 Yes Yes PWM 比較匹配 輸出功能 1 輸出 Yes Yes 0 輸出 Yes Yes 輸出保持 Yes Yes 邊沿 PWM Yes Yes 中心 PWM Yes Yes 相位計算模式 Yes,相位輸入為 TCKA/TCLKB Yes,相位輸入為 TCLKC/TCLKD 定時器緩沖操作 Yes Yes AD 轉換觸發(fā) P_TMRO_TGRA 比較匹配 P_TMR1_TGRA 比較匹配 中斷源 定時器 0 TPR 中斷 定時器 0 TGRA 中斷 定時器 0 TGRB 中斷 定時器 0 TGRC 中斷 定時器 0 PDC 中斷 定時器 0 上溢 中斷 定時器 0 下溢 中斷 定時器 1 TPR 中斷 定時器 1 TGRA 中斷 定時器 1 TGRB 中斷 定時器 1 TGRC 中斷 定時器 1 PDC 中斷 定時器 1 上溢 中斷 定時器 1 下溢 中斷 外文翻譯（譯文） 21 圖 11 PDC 定時器功能示意框圖 3 PDC 的應用 有關 PDC 的詳細介紹見《 SPMC75F2413A 編程指南》，這里我們只來研究一下 PDC在測量速度時的應用。 //Transmit captured data to DMC SPMC_DMC_Save_SpdNow(1, uiSpeed)。amp。 void IRQ6(void) { if(P_INT_Status, ) 外文翻譯（原文） 14 { if(P_UART_Status, ) MC75_DMC_RcvStream()。 Spmc75_PDCETSPD_ISR ( ) Prototype void Spmc75_PDCETSPD_ISR(void) Description Data capture, filter and calculation Input Arguments None Output Arguments None Head Files Library Files Spmc75_SPDET_V100 Note PDC ISR Example Spmc75_PDCETSPD_ISR()。 // Select FCK/64 clock source Position Detection Control Register P_POSx_DectCtrl(x = 0, 1) B15 B14 B13 B12 B11 B10 B9 B8 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 SPLCK SPLMOD SPLCNT B7 B6 B5 B4 B3 B2 B1 B0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 外文翻譯（原文） 7 PDEN SPDLY Bit 15:14 SPLCK: Sampling clock select. Select FCK/4, FCK/8, FCK/32, or FCK/128 for position sampling clock 00 = FCK/4 01 = FCK/8 10 = FCK/32 11 = FCK/128 Bit 13:12 SPLMOD: Sampling mode select. Select one of three modes: sampling when PWM signal is active (PWM is on), sampling regularly, or sampling when lower side (UN, VN, WN) phases are conducting current. 00 = Sample when UPWM/VPWM/WPWM bit is set in P_TMRx_OutputCtrl (x = 3, 4) register and generate the PWM waveform 01 = Sample regularly 10 = Sample when lower phases is in active state and conducting current 11 = Reserved Bit 11:8 SPLCNT: Sampling count select. These bits select the sampling count for the valid external position detection signals. The position signals must be sampled continuously match as many times as the sampling count set, for the position signals to be considered valid. The valid settings are from 1 to 15 times. Note that count 0 and 1 are assumed to be one time. Bit : 7 PDEN: Position detection enable. This bit enables/disables the position detection function for position input pins TIOA~C. When enabled, the input signals of these pins will be sampled and the results will be latched to PDR [2:0] bits in POS_DectData register. When disabled, PDR [2:0] will remain its status. 0 = Disable 1 = Enable Bit 6:0 SPDLY: Sampling delay. These bits set a delay time clock in which at SPLCK clock 外文翻譯（原文） 8 source. It is used to stop sampling in order to prevent erroneous detection due to noise that occurs immediately after PWM output turns on. Position detection control register When the position detection changing event occurs, the P_TMRx_TCNT (x = 0, 1) value can be transferred to TGRA. If the position detection interrupt enable bit PDCIE is set to 1 in the corresponding P_TMRx_INT (x = 0, 1) register, the PDC interrupt routine will be called to process the data. SPLCK: Select sampling clock from FCK/4, FCK/8, FCK/32, or FCK/128 for position sampling clock, which determines the detection precision of position change. Proper setting of SPLCK, SPLCNT and SPDLY will help to prevent erroneous detection and filter the disturbance. SPLMOD: Select one of these three modes: sampling when PWM signal is active (PWM is on), sampling regularly, or sampling when lower side (UN, VN, WN) phases are conducting current. SPLCNT: Sampling count select. The valid settings are from 1 to 15 times. Note that count 0 and 1 are both assumed to be one time. PDEN: This bit enables/disables the position detection function for position input pins TIOA~C. SPDLY: Sampling delay with the range of 0 to 127. The setting example is shown as blew. P_POS0_DectCtrl, = 2。 // Counting at rising edge P_TMR0_Ctrl, = 3。 TCNT is cleared every m P_POSx_DectData (x = 0, 1) changes, that is, TCNT is cleared at 外文翻譯（原文） 9 every *3m? rad rotation (m=1, 3, 6), and the position data is Ncap Since: ddt??? (Formula 1 1) and d? = *3m? , Ncapdt Fcap? Since electrical degree = p x mechanical rotation then the mechanical angular velocity is p? ?? (Formula 1 2) with the unit of rad/min. Take n as the indicator. So: 260 30nn??? ?? rad/min (Formula 1 3) n summarize: 6 0 * * 1 0 * *3 * 2 * * *F c a p m F c a p mn N c a p