【正文】 40 SMIC 典型 CMOS工藝流程 Gate Engineering Psub NWELL STI PWELL Poly PR coating Poly Mask NLDD NLDD NPKT NLDD NPKT PLDD PR PLDD PPKT Stepper Exposure NLDD Implant PLDD implant ?Poly Gate Formation : ? Poly Annealing ? PR Coating ? POLY Lithography ? Development ? POLY Gate Etching ? PR Stripping ? Thin Oxide Growth ?6. LDD (Light Dope Drain) Implant ? NLDD Lithography (Ellipsis) ? NLDD / NPKT Implant ? PLDD Lithography (Ellipsis) ? PLDD / PPKT Implant SIMIT 41 SMIC 典型 CMOS工藝流程 Drain Engineering Psub NWELL STI PWELL Poly PR coating Poly Mask NLDD NLDD NPKT NLDD NPKT PLDD PR PLDD PPKT N+ PR N+ N+ P+ PR P+ P+ Implant N+ implant ? Spacer Formation : ? PETEOS dep. ? SiN dep. ? Spacer dry etch ?Source and Drain Formation: ? N+ Lithography ? N+ implant ? PR stripping ? P+ Lithography ? P+ implant ? PR stripping SIMIT 42 SMIC 典型 CMOS工藝流程 ILD Passivation Psub NWELL STI PWELL Poly PR coating Poly Mask NLDD NLDD NPKT NLDD NPKT PLDD PR PLDD PPKT N+ PR N+ N+ P+ PR P+ SAB PSG USG ? Salicide Formation : ? SAB (Salicideblock) Oxide Dep. ? SAB Lithography (Ellipsis) ? Ti/Co Sputtering ? Salicidation RTP C49 Annealing ? TiN Residual Semitool Wet Clean ? Salicidation RTP C54 Annealing ?ILD Passivation ? SiN Deposition (Moisture And Sodium Block) ? APUSG Deposition (Gap Filling And B,P Trap) ? TEOSBPSG Deposition (Reflow And Planarization) ? ILD CMP SIMIT 43 SMIC Psub NWELL STI PWELL Poly PR coating Poly Mask NLDD NLDD NPKT NLDD NPKT PLDD PR PLDD PPKT N+ PR N+ N+ P+ PR P+ SAB PSG USG PR Coating 典型 CMOS工藝流程 Contact Plug Contact Mask PR coating Contact PR Metal 1 DUV Stepper Exposure ?Contact Plug Formation : ? Contact Lithography ? Contact Plasma Etching ? PR Strip ? Barrier Layer Deposition (Ti + TiN For Well Contact) ? RTP Annealing ? Glue Layer Deposition (Ti + TiN For Plug Adhesion) ? WCVD Filling ? WCMP ? Metal Liner Deposition (Ti + TiN For Metal Adhesion) ? Metal Sputter SIMIT 44 SMIC 典型 CMOS工藝流程 Backend (Aluminum) Psub NWELL STI PWELL Poly PR coating Poly Mask NLDD NLDD NPKT NLDD NPKT PLDD PR PLDD PPKT N+ PR N+ N+ P+ PR P+ SAB PSG USG PR Coating Contact Mask PR coating Contact PR Metal 1 Contact plug PR Coating Metal 1 mask Metal 1 PR Metal 1 HDP1 PEOX Cap Oxide PR Coating MVIA1 mask MVIA1 PRMetal 2 Stepper Exposure Stepper Exposure ?IMD Deposition ? HDPoxide Deposition ( Gap Filling) ? PEoxide Deposition ( Planarization And Uniformity) ? Imd Cmp ? Cap PEoxide ?VIA Plug Formation ?VIA Lithography Cycle ?VIA Etching And PR Strip ?Glue Layer Deposition (Ti + TiN For Plug Adhesion) ? WCVD Filling ? WCMP ? Metal Liner Deposition (Ti + TiN For Metal Adhesion) ? Metal Sputter SIMIT 45 SMIC Psub NWELL STI PWELL Poly PR coating Poly Mask NLDD NLDD NPKT NLDD NPKT PLDD PR PLDD PPKT N+ PR N+ N+ P+ PR P+ SAB PSG USG Contact plug 典型 CMOS工藝流程 Backend (Copper Dual Damascene) PR Coating Metal 1 mask Metal 1 Metal 2 Mask Stepper Exposure 2 MVIA1 MasMetal 2 Stepper Exposure 1 3? ILD/M1 Damascene ?PEOX Deposition ?M1 Lithography ?M1 Trench Etching ?M1 Cu Electroplate (ECP) ?Cu CMP ?M2/VIA1 Dual Damascene ? PEOX Deposition ?M2 Lithography ?M2 Trench Etching ?VIA1 Lithography ?VIA1 Plug Etching ?Trench Liner Deposition ?M2/VIA1 Cu ECP ?Cu CMP SIMIT 46 SMIC 銅大馬士革 (Copper Dual Damascene) SIMIT 47 SMIC 48 ? 微電子技術(shù)成就 ? MOSFET器件發(fā)展歷程 ? 典型 CMOS工藝流程模塊 ? 典型 CMOS制作工藝流程 ? MOSFET器件面臨的挑戰(zhàn) ? MOS器件結(jié)構(gòu)研究最新進(jìn)展 ? FinFET器件研究進(jìn)展 ? 可供選擇的新穎器件 短溝道效應(yīng) : 隨著 MOS器件溝道長度的不斷縮小 ， 器件的閾值電壓 Vt與溝道長度的關(guān)聯(lián)度進(jìn)一步加強(qiáng) ， 即器件的短溝道效應(yīng)將變得首先也是最嚴(yán)重的是器件的更明顯 , 需要通過改進(jìn)器件結(jié)構(gòu)加以抑制 強(qiáng)場效應(yīng) : 器件縱橫向尺寸縮小 ， 而電源電壓并不能以同樣比例縮小 ， 使得柵絕緣介質(zhì)和溝道內(nèi)場強(qiáng)不斷加強(qiáng) ， 會在器件穿通和熱電子等方面產(chǎn)生可靠性問題 多晶硅柵的耗盡效應(yīng) : 多晶硅柵的耗盡使得柵氧化層有效厚度增大 , 降低了器件的電流驅(qū)動能力 , 可以通過采用金屬柵技術(shù)加以抑制 。 SIMIT 49 SMIC 短溝道效應(yīng) (Short Channel Effect) ?For long channel device, the gate is the primary terminal in supporting the inversion charge in the channel. ?The positively ionized donor atoms on the n+ drain side of the bodydrain pn+ junction also allows for some support of inversion charge in the channel. For large devices, the contribution of the drain in controlling the inversion layer in the channel is much smaller pared to the gate. ?However, as devices are scaled down in length, the drain has a larger percentage contribution in supporting inversion charge in