非同步電路設(shè)計(存儲版)
【正文】 c1 hazard。 11. (4%)Explain transport delay and inertial delay(pp 83) (a) transport delay： 又稱為 pure delay，單純的將訊號 shift 過去，不做任何變動。 COMPONENT 4phase bundled data y z x y z x yreq xreq yack zack xack yreq zreq xreq C C Merge (wait for one) 4. (4%)Draw an asymmetric Celement and design it in transistor level. Explain its application.(510) 如果能確定電路動作中， b?一定在 a?之前， 則 b?的輸入可以省略，所以可以節(jié)省一個 transistor，增快電路速度。 (3) SG： SG 是將各狀態(tài)進(jìn)行編碼，形成 SG 內(nèi)部的 node，另外以 directed arcs 相連接，這些 arc 代表訊號的變化，因此 SG 遠(yuǎn)比 STG 複雜，但在可以用在電路合成 (synthesis)。 15. (4%)Draw two possible variable z states’ implementation templates using (simple) state holding elements.(pp 96) (1)使用 SR latch (2)使用 Celement 16. (7%)Assume variable z’ s set logic and reset logic is zset = ab and zreset=b’ c’ ,respectively. Draw the circuit in gatlevel, and show implementations in dynamic CMOS and static CMOS.(pp 100) (1) dynamic CMOS implementation (2) static CMOS implementation 17. (6%)Explain the six characteristics of STG： 1bounded, liveness, consistent state assignment, persistency, and plete state coding. (pp 88) (1) Input free choice: The selection among alternatives must only be controlled by mutually exclusive inputs. (2) 1bounded: There must never be more than one token in a place. (3) Liveness: The STG must be free from deadlocks. (4) Consistent state assignment: The transitions of a signal must strictly alternate between _ and _ in any execution of the STG. (5) Persistency: If a signal tr
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