【正文】 important, the cost of these microcontrollers is very low, making their use cost effective. In the following pages, we consider two puter CPUs, one for a plex instruction set puter (CISC) and the other for a reduced instruction set puter (RISC). After a detailed examination of the designs, we pare the performance of the two CPUs and present a brief 10 overview of some methods used to enhance that performance. Finally, we relate the design ideas discussed to general digital system design. Two CPU designs As mentioned in previous chapters, atypical CPU is usually divided into two parts: the datapath and the control unit. The datapath consists of a function unit, registers, and internal buses that provide pathways for the transfer of information between the registers, the function unit, and other puter ponents. The datapath may or may not be pipelined. The control unit consists of a program counter, an instruction register, and control logic, and may be other hardwired or microprogrammed. If the datapath is pipelined, the control unit may be also be a pipeline. The puter of which the CPU is a part is either a CISC or a RISC, with its own instruction set architecture. The purposes of this chapter is to present two CPU designs that illustrate binations of architectural characteristics of the instruction set, the datapath, and the control unit. The designs will be top down, but with the reuse of prior ponent designs, illustrating the influence of the instruction set architecture on the datapath and control units, and the influence of the datapath on the unit. The material makes extensive use of tables and diagrams. Although we reuse and modify ponent designs from others , background information from these chapters is not repeated here. References, however, are given to earlier sections of the book, where detailed information can be found. The two CPUs presented are for a CISC using a nonpipelined datapath with a microprogrammed control unit and a RICS using a pipelined datapath with a hardwired pipelined control unit. These represent two quite distinct binations of instruction set architecture, datapath, and control unit. The plex instruction set puter The first design we present is for a plex instruction set puter with a nonpipelined datapath and microprogrammed control unit. We begin by describing the instruction set architecture, including the CPU register set, instruction formats, and addressing modes. The CISC nature of the instruction set architecture is demonstrated by its memorytomemory access for data manipulation instructions, eight addressing modes, two instruction format lengths, and instructions that require significant sequences of operations for their execution. We design a datapath for implementing the CISC architecture. The datapath is based on the one initially described in Section 79 and incorporated into a CPU in section 810. modifications are made to the register file, the function unit, and the buses to support the 11 present instruction set architecture. Once the datapath has been specified, a control unit is designed to plete the implementation of the instruction set architecture. The design of the control unit must involve a coordinated definition of both the hardware organization and the microprogram organization. In particular , dividing the microprogram into microroutines, while at the same time designing the sequencer with which they interact, is a key part of the design. Even the instruction fields and opcodes are tied to this coordinated effort. Following the definition of the hardware and microcode organizations, we detail essential parts of the microcode and the microroutines for representative operations. Instruction set architecture Figure 101 shows the CISC register set accessible to the programmer. All registers have 16 bits. The register file has eight registers, R0 though is a special register that always supplies the value zero when it is used as a source and discards the result when it is used as a destination. In additional to the register file, there is a program counter PC and stack pointer SP. The presence of a stack pointer indicates that a memory stack is a part of the architecture . the final register is the processor status register PSR, which contains information only in its rightmost the five bits。我們研究任何形式的風(fēng)險，像軟件和硬件一頁提出每個解決方案。在每個執(zhí)行微線路之后，在獲取下一個指令之前該程序進(jìn)入了中斷。根據(jù)操作碼（ OPCODE）的前三個位，要么一個單一的操作，兩個操作（或者一個操作加一個參數(shù)），要么一個分支地址，這二者選其一。這個分支被圖中的五個二進(jìn)制決策框代替。這個流動顯示在圖 108 中，這個圖表并不是嚴(yán)格的 ASM 圖，因為每個矩形框?qū)?yīng)的微線路代表了不同的國家而不是一個單一的國家以及對應(yīng)的是多計時周期而不是單一的周期。SBR 被用來存儲關(guān)于 CAR 的下一代地址，同時一個微子線路是在微路線的要求下為了使微程序執(zhí)行轉(zhuǎn)向下一個微指令。其中之一是控制單元登記：指令登記 IR，程序計數(shù)器 PC 和堆棧指針度 SP。一個 2 比 1 多路復(fù)用器 MUX SO 選擇的結(jié)束位來傳遞到執(zhí)行觸發(fā)器。這個修改涉及到切換邏輯的最終的位。在微指令中有 5 位的空間是用來合并目的地和來源地址的 DSA，再增加 5位空間給 B 地址 SB。 我們不能進(jìn)入 8個基于在指令集內(nèi)可用 3 位登記地址的臨時登記冊。 在第 810節(jié)里，注冊 R8是被作為臨時的存儲位置。例如， LD, ST, IN, 和 OUT 都可以通過使用在內(nèi)存映射結(jié)構(gòu)里的 MOVE 指令來實現(xiàn)。 帶有 IR(15:14)=11 的指令是分流的。表格的第三欄提供了注冊轉(zhuǎn)換為針對一個操作指令的每個處理模式的聲明。對帶有單一運(yùn)算的 16 位指令來說有足夠的 OPCODE 位。右邊的 4 個 OPCODE 位可以指定多達(dá) 16 個 3 操作或帶有暗示的操作地址。通用指令格式的有五個領(lǐng)域。堆棧指針的出現(xiàn)的情況表 明內(nèi)存堆棧是構(gòu)架的一部分。特別是把微程序分成微線路，然而同時也設(shè)計了它們相互影響的音序器，這是設(shè)計的關(guān)鍵部分。 2．復(fù)雜指令集計算機(jī) 我們提交的第一個設(shè)計就是為一個帶有非流水線數(shù)據(jù)路徑和微程序的控制單元的 復(fù)雜指令集計算機(jī)而設(shè)計的。電腦的 CPU 是一個部分，要么是復(fù)雜指令集計算機(jī)（ CISC），要么是精簡指令集計算機(jī)（ RISC），有自己的指令 1 集架構(gòu)。 在接下去的幾頁里，我考慮的是兩個計算機(jī) 的 CPU，一個是一個復(fù)雜指令集計算機(jī)（ CISC），另一個是精簡指令集計算機(jī)（ RISC）。在外部， CPU 為轉(zhuǎn)換指令數(shù)據(jù)和控制信息提供一個或多個總線并從組件連接到 它。字長也許更短，（或者說 4或 8個字節(jié)），編制數(shù)量少，指令集有限。這個數(shù)據(jù)途徑有可能是流水線，也有可能不是。但是，參考資料可以在這本書的前幾節(jié)里找到詳細(xì)的信息。對登記檔案，功能單元以及總線進(jìn)行修改來支持現(xiàn)有的指令集構(gòu)架。這個注冊文件有 8 個寄存器，從 R0 到 R7。根據(jù)一些明確的操作和是否分開操作，將這些操作分成 4 組。 圖 2 OPCODE 的前兩位， IR（ 15： 14），確定了一些明確的操作和格式領(lǐng)域的如何使用。但是，切換指令要求有一個切換數(shù)額來只是到底切換多少位。否則，如果第三位等于 0 的，間接處理就不適用，而如果等于 1 ，間接處理就適用。如果 S等于 1 那么目的地使用處理方式，且來源是注冊的。在第 9章里給出的大部分操作都被包括在指令集里。 數(shù)據(jù)路徑組織 不是從頭開始，我們將重新使用非流水線數(shù)據(jù)路徑被雇用在第 810 節(jié)里的微程序控制器，并進(jìn)行修改。圖 3提供了一個帶有臨時登 記屏蔽的擴(kuò)展注冊文件的地圖。該登記冊檔案使用 B 地址的來