【正文】 at this feature is not demonstrated in the sample QuickLogic FPGA design. Finally, frequency modulation is a given with the basic NCO design. The frequency port can directly adjust the carrier output frequency. Since frequency words are loaded into the DDS synchronous to the sample clock, frequency changes are phase continuous. Although DDS systems give the designer plete control of plex modulation synthesis, the representation of sinusoidal phase and magnitude in a nonlinear digital format introduces new design plexities. In sampling any continuoustime signal, one must consider the sampling theory and quantization error. To understand the effects of the sampling theory on a DDS system, it is best to look at the DDS synthesis processes in both the time and frequency domain. As stated above, the NCO generates a sinusoidal wave form by accumulating the phase at a specified rate and then uses the phase value to address a ROM table of sinusoidal amplitude values. Thus, the NCO is essentially taking a sinusoidal wave form and sampling it with the rising or falling edge of the NCO input reference sampling clock. Figure 4 shows the time and frequency domain of the NCO processing. Note that this representation does not assume quantization. Based on the loaded frequency word, the NCO produces a set of amplitude output values at a set period. The frequency domain representation of this sinusoid is an impulse function at the specified frequency. The NCO, however, outputs discrete digital samples of this sinusoid at the NCO reference clock rate. In the time domain, the NCO output is a function of the sampling clock edge strobes multiplied by the sinusoid wave form producing a train of impulses at the sinusoid amplitude. In the frequency domain, the sampling strobes of the reference clock produce a train of impulses at frequencies of K times the NCO clock frequency where K = ... 1, 0, 1, 2 .... Since the sampling clock was multiplied by the sinusoid in the time domain, the frequency domain ponents of the sinusoid and the sampling clock need to be convolved to produce the frequency domain representation of the NCO output. The frequency domain results are the impulse function at the fundamental frequency of the sinusoid and the alias impulse functions occurring at K times the NCO clock frequency plus or minus the fundamental frequency. The fundamental and alias ponent occur at: K*Fclk Fout K*Fclk + Fout Where K = ... 1, 0 , 1, 2 ..... and K = 0 is the NCO sinusoid fundamental frequency Fout is the specified NCO sinusoid output frequency Fclk is the NCO reference clock frequency FIGURE 4 NCO Output Representation Time and Frequency Domain The DAC of the DDS system takes the NCO output values and translates these values into analog voltages. Figure 4 shows the time and frequency domain representations of the DAC processing starting with the NCO output. The DAC output is a sample and hold circuit that takes the NCO digital amplitude words and converts the value into an analog voltage and holds the value for one sample clock period. The time domain plot of the DAC processing is the convolution of the NCO sampled output values with a pulse of one sample clock period. The frequency domain plot of the sampling pulse is a sin(x)/x function with the first null at the sample clock frequency. Since the time domain was convolved, the frequency domain is multiplied. This multiplication dampens the NCO output with the sin(x)/x envelope. This attenuation at the DAC output can be calculated as follows and a sample output spectrum is shown in Figure 5: Atten(F) = 20log[(sin(pF/Fclk)/pF/Fclk)] Where F is the output frequency Fclk is the sample clock frequency FIGURE 5: DAC Output Representation in Time and Frequency Domain Aside from the sampling theory, the quantization of the real values into digital form must also be considered in the performance analysis of a DDS system. The spurious response of a DDS system is primarily dictated by two quantization parameters. These parameters are the phase quantization by the phase accumulator and the magnitude quantization by the ROM sinusoidal table and the DAC. As mentioned above, only the upper Y bits of the phase accumulator are used to address the ROM lookup table. It should be noted, however, that using only the upper Y bits of the phase accumulator introduces a phase truncation. When a frequency word containing a nonzero value in the lower (NY1:0) bits is loaded into the DDS system, the lower nonzero bits will accumulate to the upper Y bits and cause a phase truncation. The frequency at which the phase truncation occurs can be calculated by the following: Ftrunc = FW(NY 1:0)/2NY* Fclk. A phase truncation will periodically (at the Ftrunc rate) phase modulate the output carrier forward 2p/28 to pensate for frequency word granularity greater than 2Y. The phase jump caused by the accumulation of phase truncated bits produces spurs around the fundamental. These spurs are located plus and minus the truncation frequency from the fundamental frequency and the magnitude of the spurs will be 20log(2Y)dBc. A sample output of a phase truncation spur is shown in Figure 5. In a typical NCO design, the ROM sinusoidal table will hold a 188。一個(gè)適合這個(gè)目標(biāo)的數(shù)字式設(shè)計(jì)就是直接數(shù)字頻率合成器（ DDS）。 一個(gè)基本的 DDS 系統(tǒng)包括一個(gè)數(shù)字振蕩器（ NCO）用來產(chǎn)生輸出載波，和一個(gè)數(shù)模轉(zhuǎn)換器（ DAC）用來將從 NCO 過來的數(shù)字式正弦曲線字產(chǎn)生一個(gè)抽樣的模擬載波。 這個(gè)頻率控制字是最后一個(gè)抽樣相位值通過一個(gè) N 位加法器的連 續(xù)地累加而成。 因?yàn)橐粋€(gè) NCO 輸出的一個(gè)基于一個(gè)數(shù)字表示的相位和正弦波量化形式的載波，所以設(shè)計(jì)者可以完全的控制輸出載波的頻率，相位和幅度。 為了理解 DDS 系統(tǒng)中取樣理論的效果，最好看一下時(shí)間和頻率域的 DDS 合成過程。在時(shí)間域里， NCO輸出是一個(gè)取樣時(shí)鐘邊緣閘門乘于正弦波形式產(chǎn)生的一個(gè)推動(dòng)序列正弦振幅的作用。 DAC 過程的時(shí)域結(jié)構(gòu)是 NCO 抽樣輸出值和一個(gè)抽樣周期脈沖的卷積。 如上所示，相位累加器只有高 Y 比特是用來尋址 ROM 表。ROM表是通過把所有可能的相位值地址和映射到實(shí)際正弦波大小的近似 D比特來產(chǎn)生的。 微分線性是指輸出的步進(jìn)大小為比特到比特。超出輸出范圍時(shí)一個(gè) DAC會(huì)有一個(gè)特有的彎曲特性曲線。 積分線性是一個(gè) DAC的總的線性性 能對(duì)一個(gè)理想的線性直線的一個(gè)衡量。DAC的量化曲線數(shù)字輸入對(duì) 應(yīng)模擬輸出的 DAC量化曲線