mcs51單片機(jī)英文文獻(xiàn)及翻譯-免費(fèi)閱讀
【正文】 作為恢復(fù)到電路，其功能是非常重要的。其主要功能是把最初的 PC 為0000H，使單芯片電腦開始持有單位 0000H 開始執(zhí)行程序的行為。法令： Q=1 時，可以輸出 W 線路信號，在制定方案的時候，那就是第一個函數(shù)仍是第二個功能，但不必軟件預(yù)先設(shè)置 P3 口。另一條是它可以導(dǎo)致在來兩個工作狀態(tài)密切，使其電阻值變化近似 0 或 2 阻值的情況非常嚴(yán)重。熟悉 I/O端口的邏輯電路，不僅有助于正確和合理利用端口，并在一定程度上將有助于設(shè)計(jì)周邊的單芯片計(jì)算機(jī)的邏輯電路。 8051 單芯片的電腦有 4 個 8 步行并進(jìn)的 I/O 端口，分別為 P0,P1,P2和 P3。在訪問內(nèi)存，相應(yīng)的，只有一個地址的內(nèi)存單 元，可以用外部存儲，也可以內(nèi)存，并通過訪問順序與此類似。這種脈沖信號，作為 8051 的工作，即單位時間的最低基本節(jié)奏。其中 CPU 是一個芯片計(jì)算機(jī)的核心，它是計(jì)算機(jī)的指揮中心，是由算術(shù)單元和控制器等部分組成。 一個單芯片的計(jì)算機(jī)是由以下幾個部分組成：（ 1）一個 8 位的微處理器（ CPU）。clock, can output W line signal. At the time of programming, it is that the first function is still the second function but needn39。 南 京 工 程 學(xué) 院 畢業(yè)設(shè)計(jì)文獻(xiàn)資料翻譯 （原文及譯文） 原文名稱： Structure and function of the MCS51 series 課題名稱： 基于單片機(jī)的交通燈控制系統(tǒng) 學(xué)生姓名： 吳茜茜 學(xué) 號： 240072310 指導(dǎo)老師： 宋 紅 梅 所在系部： 康尼學(xué)院 專業(yè)名稱： 通信工程 2020 年 3 月 南 京 Structure and function of the MCS51 series Structure and function of the MCS51 series onechip puter MCS51 is a name of a piece of onechip puter series which Intel Company produces. This pany introduced 8 topgrade onechip puters of MCS51 series in 1980 after introducing 8 onechip puters of MCS48 series in 1976. It belong to a lot of kinds this line of onechip puter the chips have, such as 8051, 8031, 8751, 80C51BH, 80C31BH,etc., their basic position, basic performance and instruction system are all the daily representatives51 serial onechip puters. A onechip puter system is made up of several following parts: (1) One microprocessor of 8 (CPU). ( 2) At slice data memory RAM (128B/256B),it use not depositing not can reading /data that write, such as result not middle of operation, final result and data wanted to show, etc. (3) Procedure memory ROM/EPROM (4KB/8KB ), is used to preserve the procedure , some initial data and form in slice. But does not take ROM/EPROM within some onechip puters, such as 8031, 8032.(4) Four 8 run side by side I/O interface P0 four P3, each mouth can use as introduction , may use as exporting too. (5) Two timer / counter, each timer / counter may set up and count in the way, used to count to the external incident, can set up into a timing way too, and can according to count or result of timing realize the control of the puter. (6) Five cut off cutting off the control system of the source. (7) One all duplex serial I/O mouth of UART (universal asynchronous receiver/transmitter (UART) ), is it realize onechip puter or onechip puter and serial munication of puter to use for. (8) Stretch oscillator and clock produce circuit, quartz crystal finely tune electric capacity need outer. Allow oscillation frequency as 12 megahertz now at most. Every the abovementioned part was joined through the inside data bus .Among them, CPU is a core of the onechip puter, it is the control of the puter and mand centre, made up of such parts as arithmetic unit and controller , etc.. The arithmetic unit can carry on 8 persons of arithmetic operation and unit ALU of logic operation while including one, the 1 storing device temporaries of 8, storing device 2 temporarily, 839。t have software that set up P3 mouth in advance .It hardware not inside is the automatic to have two function outputted when CPU carries on SFR and seeks the location to visit to P3 mouth/at not lasting lining, there are in
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