【正文】 本文還證明了把硬度量化成固化工藝的測試方法。在這 庫，節(jié)點分離是幾微米。 CMOS超低功耗輻射容錯設(shè)備使用的方案是基于單粒子防護技術(shù)元件容錯輸入性質(zhì)，此時多余的輸入數(shù)據(jù)是提供給單獨的存儲節(jié)點。 B．單粒子翻轉(zhuǎn) CMOS超低功耗輻射容錯 設(shè)備使用的存儲單元的一級結(jié)構(gòu)是單粒子防護技術(shù)（ SERT） [ 5 ] 。如果被測設(shè)備遇到了一個錯誤，不能中斷功能（例如，數(shù)據(jù)寄存器不匹配）通過描述的錯誤串口有發(fā)出一個更多的長篇報告，并繼續(xù)進行測試。然后啟動電路，同時進行兩個功能： 被測設(shè)備的復(fù)位線保持有效一段時間（ 大約 10毫秒） ； 并且，駐存在程序碼 RAM的測試代碼映射到地址 0x0000 （在被測設(shè)備計算機內(nèi)存空間該可擦寫可編程只讀存儲器將不再被 訪問）。 特殊功能寄存器（ SFR） 這項測試使用可特殊功能寄存器 21位中的 12位的已知靜態(tài)值，然后不斷地比較已知值與當(dāng)前值。 存儲器 這項測試間接地用 0x55模式裝在內(nèi)部數(shù)據(jù)存儲器的地址 D： 0x20到 D：0xff （或 D ： 0x20到 D： 0x080為 CMOS超低功耗輻射容錯 被測設(shè)備）。 ? 看門狗，必要時為 8051正常運行和重新啟動的可視化確認提供測試代碼。因為每個試驗是獨立的，他們是獨立加載的，在被測設(shè)備也是相互獨立執(zhí)行的。這種“被測設(shè)備板”是由短 60導(dǎo)體帶狀電纜連接到“主板”。不同于器件工作所固有的 功能，這些功能沒有被利用是為了達拉斯和英特爾的測試代碼最大限度地相似。他們工作環(huán)境是額定電壓 +5伏，溫度范圍 在 0至 70 176。 技術(shù)性能的評價是為測試微控制器開發(fā)硬件和軟件。有許多工業(yè)供應(yīng)商，他們供應(yīng)這種控制器或把這種控制器集成到某種類型的系統(tǒng)芯片的結(jié)構(gòu)。如果所有這些因素都已經(jīng)具備或測試芯片已被驗證，那么測試就沒有必要了。 9個月后，美國航天局飛行項目就會使用賣主 A的程序庫設(shè)計了新器件進行組合了。然而，擁有最先進的技術(shù)的工業(yè)用抗輻射加固微電子器件，幾代產(chǎn)品中都有相對局限性， 所以 美國航天局的這一任務(wù)很有挑戰(zhàn)性。s functionality. Thus, if the test ran without a Single Event Functional Interrupt (SEFI) either the DUT Computer itself or the Test Controller could have terminated the test and allowed the posttest functions to be executed. If a SEFI occurred, the Test Controller forced a reboot into Boot/Serial Loader code and then executed the posttest functions. During any test of the DUT, the DUT exercised a portion of its functionality (., Register operations or Internal RAM check, or Timer operations) at the highest utilization possible, while making a minimal periodic report to the Test Control Computer to convey that the DUT Computer was still functional. If this report ceased, the Test Controller knew that a SEFI had occurred. This periodic data was called telemetry. If the DUT encountered an error that was not interrupting the functionality (., a data register mispare) it sent a more lengthy report through the serial port describing that error, and continued with the test. VIII. DISCUSSION A. Single Event Latchup The main argument for why latchup is not an issue for the CULPRiT devices is that the operating voltage of volts should be below the holding voltage required for latchup to occur. In addition to this, the cell library used also incorporates the heavy dual guardbarring scheme [4]. This scheme has been demonstrated multiple times to be very effective in rendering CMOS circuits pletely immune to SEL up to test limits of 120 MeVcm2/mg. This is true in circuits operating at 5, , and Volts, as well as the Volt CULPRiT circuits. In one case, a 5 Volt circuit fabricated on noncircuits wafers even exhibited such SEL immunity. B. Single Event Upset The primary structure of the storage unit used in the CULPRiT devices is the Single Event Resistant Topology (SERT) [5]. Given the SERT cell topology and a single upset node assumption, it is expected that the SERT cell will be pletely immune to SEUs occurring internal to the memory cell itself. Obviously there are other things going on. The CULPRiT 8051 results reported here are quite similar to some results obtained with a CULPRiT CCSDS lossless pression chip (USES) [6]. The CULPRiT USES was synthesized using exactly the same tools and library as the CULPRiT 8051. With the CULPRiT USES, the SEU cross section data [7] was taken as a function of frequency at two LET values, and MeVcm2/mg. In both cases the data fit well to a linear model where cross section is proportional to clock. In the LET case, the zero frequency intercept occurred essentially at the zero cross section point, indicating that virtually all of these SEUs are captured SETs from the binational logic. The LET data indicated that the SET (frequency dependent) ponent is sitting on top of a dcbias ponent – presumably a second upset mechanism is occurring internal to the SERT cells only at a second, higher LET threshold. The SET mitigation scheme used in the CULPRiT devices is based on the SERT cell39。Validation and Testing of Design Hardening for Single Event Effects Using the 8051 Microcontroller Abstract With the dearth of dedicated radiation hardened foundries, new and novel techniques are being developed for hardening designs using nondedicated foundry services. In this paper, we will discuss the implications of validating these methods for the single event effects (SEE) in the space environment. Topics include the types of tests that are required and the design coverage (., design libraries: do they need validating for each application?). Finally, an 8051 microcontroller core from NASA Institute of Advanced Microelectronics (IAμE) CMOS Ultra Low Power Radiation Tolerant (CULPRiT) design is evaluated for SEE mitigative techniques against two mercial 8051 devices. Index Terms Single Event Effects, HardenedByDesign, microcontroller, radiation effects. I. INTRODUCTION NASA constantly strives to provide the best capture of science while operating in a space radiation environment using a minimum of resources [1,2]. With a relatively limited selection of radiationhardened microelectronic devices that are often two or more generations of performance behind mercial stateoftheart technologies, NASA’s performance of this task is quite challenging. One method of alleviating this is by the use of mercial foundry alternatives with no or minimally invasive design techniques for hardening. This is often called hardenedbydesign (HBD).Building customtype HBD devices using design libraries and automated design tools may provide NASA the solution it needs to meet stringent science performance specifications in a timely, costeffective, and reliable manner. However, one question still exists: traditional ra