【正文】 each phase shift can represent two signal elements. The AD9830, AD9831, AD9832, and AD9835 provide four phase registers to allow plex phase modulation schemes to be implemented by continuously updating different phase offsets to the registers. Can multiple DDS devices be synchronized for, say, IQ capability?It is possible to use two single DDS devices that operate on the same master clock to output two signals whose phase relationship can then be directly controlled. In Figure 8, two AD9834s are programmed using one reference clock, with the same reset pin being used to update both parts. Using this setup, it is possible to do IQ modulation.MCLKRESETAD9834AD9834PHASESHIFTFigure 8. Multiple DDS ICs in synchronous mode.4 Analog Dialogue 3808, August (2020)A reset must be asserted after powerup and prior to transferring any data to the DDS. This sets the DDS output to a known phase, which serves as the mon reference point that allows synchronization of multiple DDS devices. When new data is sent simultaneously to multiple DDS units, a coherent phase relationship can be maintained, and their relative phase offset can be predictably shifted by means of the phaseoffset register. The AD9833 and AD9834 have 12 bits of phase resolution, with an effective resolution of degree. [For further details on synchronizing multiple DDS units please see Application Note AN605.] What are the key performance specs of a DDS based system?Phase noise, jitter, and spuriousfree dynamic range (SFDR). Phase noise is a measure (dBc/Hz) of the shortterm frequency instability of the oscillator. It is measured as the singlesideband noise resulting from changes in frequency (in decibels below the amplitude at the operating frequency of the oscillator using a 1Hz bandwidth) at two or more frequency displacements from the operating frequency of the oscillator. This measurement has particular application to performance in the analog munications industry.Do DDS devices have good phase noise?Noise in a sampled system depends on many factors. Referenceclock jitter can be seen as phase noise on the fundamental signal in a DDS system。 and phase truncation may introduce an error level into the system, depending on the code word chosen. For a ratio that can be exactly expressed by a truncated binarycoded word, there is no truncation error. For ratios requiring more bits than are available, the resulting phase noise truncation error results in spurs in a spectral plot. Their magnitudes and distribution depends on the code word chosen. The DAC also contributes to noise in the system. DAC quantization or linearity errors will result in both noise and harmonics. Figure 9 shows a phase noise plot for a typical DDS device—in this case an AD9834.FREQUENCY (Hz)dBc/Hz–100–110–120–130–140–150–160100 1k 10k 100k 200kAVDD= DVDD= 3VTA= 25CFigure 9. Typical output phase noise plot for the AD9834. Output frequency is 2 MHz and M clock is 50 MHz.What about jitter?Jitter is the dynamic displacement of digital signal edges from their longterm average positions, measured in degrees rms. A perfect oscillator would have rising and falling edges occurring at precisely regular moments in time and would never vary. This, of course, is impossible, as even the best oscillators are constructed from real ponents with sources of noise and other imperfections. A highquality, lowphasenoise crystal oscillator will have jitter of less than 35 picoseconds (ps) of period jitter, accumulated over many millions of clock edgesJitter in oscillators is caused by thermal noise, instabilities in the oscillator electronics, external interference through the power rails, ground, and even the output connections. Other influences include external magic or electric fields, such as RF interference from nearby transmitters, which can contribute jitter affecting the oscillator’s output. Even a simple amplifier, inverter, or buffer will contribute jitter to a signal.Thus the output of a DDS device will add a certain amount of jitter. Since every clock will already have an intrinsic level of jitter, choosing an oscillator with low jitter is critical to begin with. Dividing down the frequency of a highfrequency clock is one way to reduce jitter. With frequency division, the same amount of jitter occurs within a longer period, reducing its percentage of system time. In general, to reduce essential sources of jitter and avoid introducing additional sources, one sho