【正文】 etch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12volt programming enable voltage ( VPP ) during Flash programming when 12volt programming is selected. Port 3: Port 3 is an 8bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL ) because of the pullups. Port 3 also serves the functions of various special features of the AT89C51, as shown in the following table. Port 3 also receives some control signals for Flash programming and verification. Port Pin Alternate Function RXD (serial input port) TXD（ serial output port） external interrupt 0 external interrupt 1 T0(timer 0 external input) T1(timer 1 external input） external data memory write strobe external data memory read strobe GND: Ground. VCC: Supply voltage. Port 2: Port 2 is an 8bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current ( IIL )because of the internal pullups. Port 2 emits the highorder address byte during fetches from external program memory and during accesses to external data memory that use 16bit addresses (MOVX DPTR). In this application, Port 2 uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8bit addresses (MOVX RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the highorder address bits and some control signals during Flash programming and verification. PSEN : Program Store Enable is the read strobe to external program memory. When the AT89s52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. 功能特性概述 AT89s52提供以下標準功能： 8K 字節(jié) Flash閃速存儲 器， 256字節(jié)內部 RAM，32個 I/O 口線， 3個 16位定時 /計數器，一個 6向量兩級中斷結構，一個全雙工串行通信口，片內振蕩器及時鐘電路。引腳功能說明如下： 作為輸出口用時，每位能吸收電流的方式驅動 8 個 TTL 邏輯門電路，對 端口 P0寫 “1”時，可作為高阻抗輸入端用。P1口： P1是一個帶內部上拉電 阻的 8位雙向 I/O 口， P1的輸出緩沖級可驅動(吸收或輸出電流 )4 個 TTL 邏輯門電路。 Flash變成和程序校驗時， P1接收低 8位地址。在訪問外部程序存儲器或 16位地址的外部數據存儲器 (例如執(zhí)行 MOVXDPTR 指令 )時， P2 口送出高 8 位地址數據。P3 口： P3 時一組倒有內部上拉電阻的 8 位雙向 I/O 口。P3口除了作為一般的 I/O 口線外，更重要的用途時它的第二功能，如表 2。當振蕩器工作時， RST 引腳出現兩個機器周期以上高電平將使單片機復位。要注意的是：每當訪問外部數據存儲器時將跳過一個 ALE脈沖。此外，該引腳會被微弱拉高，單片機執(zhí)行外部程序 時，將跳過兩次 PROG 信號。 如 EA端為高電平 (接 VCC 端 )， CPU則執(zhí)行內部程序存儲器中的指令。 外接 石英晶體 (或陶瓷諧振器 )及電容 C C2接在放大器的反饋回路中構成并聯振蕩電路。這種情況下，外部時鐘脈沖接到 XTAL1端，即內部時鐘發(fā)生器的輸入端， XTAL2則懸空。空閑模式可由任何允許的中斷請求或硬件復位終止。為了避免可能對端口產生以外寫入，激活空閑模式的那條指令后一條指令不應該是一條對端口或外部存儲器的寫入指令。 程序加密位 保護類型 LB1 LB2 LB3 1 U U U 沒有程序保護功能 2 P U U 禁止從外部程序存儲器中執(zhí)行 MOVC 指令讀取內部程序存儲器的內容 3 P P U 除上表功能外，還禁止程序校驗 4 P P P 除以上功能外，同時禁止外部執(zhí)行 當 加密位 LB1 被編程時，在復位期間， EA 端的邏輯電平被采樣并鎖存，如果單片機上電后一直沒有復位，則鎖存起的初始值是一個隨機數，且這個隨機數會一直保持到真正復位為止。編程接口可接收高電平 (+12V)或低電平 (VCC)的允許編程信號，低電平編程模式適合于用戶再線編程系統(tǒng)，而高電平編程模式可與通用 EPROM編程器兼容。 2．在數據線上加上要寫入的數據字節(jié)。每個字節(jié)寫入周期是自身定時地，通常約為 。編程完成后， 。 芯片擦除： 利用控制信號的正確組合 (表 1)并保持 ALE/^PROG 引腳 10ms 的低電平脈沖寬度即可將 PEROM陣列 (4k字節(jié) )整片擦除，代碼陣列在擦除操作中將任何非空單元 寫入 “1”，這步驟需要再編程之前進行。 (031H)=51H聲明為 at89s52單片機。