【正文】 once to program a byte in the Flash array or the lock bits. The bytewrite cycle is selftimed and typically takes no more than ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. Data Polling: The at89s52 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the plement of the written datum on . Once the write cycle has been pleted, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated. Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. is pulled low after ALE goes high during programming to indicate BUSY. is pulled high again when programming is done to indicate READY. Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled. Chip Erase: The entire Flash Programmable and Erasable Read Only Memory array is erased electrically by using the proper bination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be reprogrammed. Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that and must be pulled to a logic low. The values returned are as follows. (030H) = 1EH indicates manufactured by Atmel (031H) = 51H indicates 89C51 (032H) = FFH indicates 12V programming (032H) = 05H indicates 5V programming Programming Interface: Every code byte in the Flash array can be written and the entire array can be erased by using the appropriate bination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to pletion. 中文翻譯 AT89S52 AT89s52是美國 ATMEL公司生產(chǎn)的低功耗，高性能 COMS 8位單片機，片內(nèi)含 8K bytes的可反復擦寫的 Flash只讀程序存儲器和 256 bytes的隨機存取數(shù)據(jù)存儲器 (RAM)，器件采用 ATMEL公司的高密度、非易是失性存儲技術(shù)生產(chǎn)，與標準MCS－ 51 指令系統(tǒng)及 8052 產(chǎn)品引腳兼容，片內(nèi)置通用 8 位中央處理器 (CPU)和Flash存儲單元，功能強大 AT89s52單片機適用許多較為復雜控制應(yīng)用場合。EA /VPP: External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12volt programming enable voltage ( VPP ) during Flash programming when 12volt programming is selected. ALE/ PROG : Address Latch Enable is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG ) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALEdisable bit has no effect if the microcontroller is in external execution mode. Port 3: Port 3 is an 8bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Po