【正文】 hour0,hour1 : buffer std_logic_vector(3 downto 0)。sec0,sec1 : buffer std_logic_vector(3 downto 0)。a0,a1,b0,b1,c0,c1 : out std_logic_vector(3 downto 0)。use 。end Behavioral。event and clkn=39。end yearth1。use 。use 。)thenif mon2=“0001” AND mon1=“0010” then mon2elsif mon1=“1001” then mon2else mon1end if。139。mon2,mon1 : inout std_logic_vector(3 downto 0)。use 。end Behavioral。139。architecture Behavioral of date1 isbeginProcess(clkd,set)Beginif set=39。entity date1 isPort(clkd,set : in std_logic。use 。End process。event and clkh=39。139。hor2,hor1 : inout std_logic_vector(3 downto 0)。use 。end Behavioral。139。 then min2Elsif set=39。enmin : out std_logic)。Unment the following lines to use the declarations that areprovided for instantiating Xilinx primitive UNISIM。分顯示模塊 library IEEE。)thenif sec2=“0101” AND sec1=“1001” then sec2elsif sec1=“1001” then sec2else sec1end if。139。end secute1。use 。use 。END PROCESS。SIGNAL STX:state。entity mux isPort(clk,ina,inb,sel,Reset : in std_logic。use 。END PROCESS REG2。139。END PROCESS。end mux1。Unment the following lines to use the declarations that areprovided for instantiating Xilinx primitive UNISIM。顯示切換程序 library IEEE。 thenCASE STX ISWHEN st0=STXWHEN st1=STXWHEN st2=STXWHEN st3=STXWHEN st4=STXWHEN st5=STXWHEN st6=STXWHEN st7=STXEND CASE。139。END PROCESS COM1。architecture Behavioral of mux3 isTYPE states IS(st0, st1, st2, st3, st4, st5, st6, st7)。entity mux3 isPort(clk,Reset,sel : in std_logic。use 。6）計時器（year）是由一個60進制的計數(shù)器構成的，具有清0、置數(shù)和計數(shù)功能。其中reset為清0信號，當reset為0時，星期計時器清0；set 為置數(shù)信號，當set為0時，星期計時器置數(shù)，置d1的值。3）時計時器（hour）是由一個24進制的計數(shù)器構成的，具有清0、置數(shù)和計數(shù)功能。clk為驅(qū)動秒計時器的時鐘，sec為秒計時器的輸出，ensec為秒計時器的進位信號，作為下一級的時鐘輸入信號。 then temp2temp1第二篇：用狀態(tài)機實現(xiàn)的EDA多功能數(shù)字鐘課程設計VHDL代碼設計并實現(xiàn)具有一定功能的數(shù)字鐘該數(shù)字鐘可以實現(xiàn)3個功能：計時功能、整點報時功能和重置時間功能，因此有3個功能：計時、重置時間、復位。end yearcounter。entity yearcounter isport（clk: in std_logic。library ieee。u3:monthcounter port map(qcday,monthset,monthin,smonth,qcmonth)。signal smonth,syear:std_logic_vector(7 downto 0)。end ponent。day28: out std_logic。end ponent。set3:out std_logic。setlap: in std_logic_vector(1 downto 0)。year_in: in std_logic_vector(7 downto 0)。qc: out std_logic)。ponent monthcounterport（clk: in std_logic。day29: in std_logic。day_in: in std_logic_vector(7 downto 0)。月輸出year: out std_logic_vector(7 downto 0)年輸出)。調(diào)整信號setlap: in std_logic_vector(1 downto 0)。architecture arch of weekcounter is signal temp:std_logic_vector(3 downto 0)。process(qc3)begin if rising_edge(qc3)then flagport（clk: in std_logic。begin u1:counter99 port map(clk,start_stop,reset,tcentsec,qc1)。qc: out std_logic)。end ponent。en: in std_logic。百分秒輸出，當超過60分轉為秒sec: out std_logic_vector(7 downto 0)。139。分和秒輸出qc:out std_logic進位)。139。月輸出qc: out std_logic進位)。then temp2temp1port（clk: in std_logic。end hourcounter。計數(shù)脈沖set:in std_logic。u2:sec_mincounter port map(clk,secset,secin,sec,qcsec)。signal secset,minset,hourset: std_logic。q1: out std_logic_vector(7 downto 0)。d: in std_logic_vector(7 downto 0)。qc:out std_logic)。ponent hourcounter port（clk: in std_logic。d:in std_logic_vector(7 downto 0)。整點報時qc: out std_logic進位)。調(diào)整輸入sec:out std_logic_vector(7 downto 0)。 then case setlap is when“00”=set1q1set1q2set1q3set1port（clk: in std_logic。q3: out std_logic_vector(7 downto 0))。set2:out std_logic。then disdisdisdisdisglisten(1 downto 0)glisten(5 downto 2)glisten(3 downto 2)glisten(5 downto 4)glisten(1 downto 0)glisten(5 downto 4)glisten(3 downto 0)glistenport（set:in std_logic。顯示輸出glisten:out std_logic_vector(5 downto 0)閃爍輸出)。閃爍位選擇watch: in std_logic_vector(23 downto 0)。when “00000011”=day28day28day28day28day28day28day28day28day28day28day28port（module: in std_logic_vector(2 downto 0)。039。該位為1表示該月為29天day30: out std_logic。 then temp2year2: in std_logic。139。139。end daycounter。進位day28: in std_logic。計數(shù)脈沖set: in std_logic。architecture arch of counter99 is signal temp1,temp2:std_logic_vector(3 downto 0)。計數(shù)使能clr: in std_logic。begin process(clr,clk)begin if clr=39。復位q: out std_logic_vector(7 downto 0)。begin process(mode,setclk)begin if mode=39。功能選擇脈沖module: out std_logic_vector(2 downto 0)功能輸出)。architecture arch of adjust is signal temp2,temp1:std_logic_vector(3 downto 0)。u7:weekcounter port map(qc,weekclk,weekout)。u3:stopwatch port map(clk100,reset,start_stop,mcentsec,msec,mmin)。signal qc:std_logic。end ponent。time:in std_logic_vector(23 downto 0)。showdate:in std_logic。month: out std_logic_vector(7 downto 0)。set: in std_logic。qh:out std_logic。d:in std_logic_vector(7 downto 0)。end ponent。start_stop: in std_logic。q: out std_logic_vector(3 downto 0))。module: out std_logic_vector(2 downto 0))。end ponent。星期輸出qh:out std_logic整點報時)。功能選擇脈沖showdate:in std_logic。秒表啟動/停止控制reset:in std_logic。entity clock is port(clk1hz:in std_logic。use 。星期調(diào)整脈沖start_stop:in std_logic。調(diào)整位選擇脈沖mode:in std_logic。閃爍指示weekout:out std_logic_vector(3 downto 0)。data_in: out std_logic_vector(7 downto 0))。mode: in std_logic。clk2: in std_logic。reset: in std_logic。min: out std_logic_vector(7 downto 0))。setlap: in std_logic_vector(1 downto 0)。hour:out std_logic_vector(7 downto 0)。ponent y_m_d_countport（clk: in std_logic。day: out std_logic_vector(7 downto 0)。ponent displayport（module: in std_logic_vector(2 downto 0)。watch: in std_logic_vector(23 downto 0)。glisten:out std_logic_vector(5 downto 0))。signal module:std_logic_vector(2 downto 0)。u2:control port map(setselect,setlap,mode,module)。u6:display port map(module,showdate,clk1hz,setlap,watch,time,date,dis,glisten)。end adjust。調(diào)整位選擇脈沖mode: in std_logic。signal s:std_logic_vector(3 downto 0)。計數(shù)脈沖clr: in std_logic。architecture arch of counter60 is signal temp1,temp2:std_logic_vector(3 downto 0)。100vhz計數(shù)脈沖en: in std_logic。end counter99。then temp1temp1port（clk: in std_logic。天輸出qc: out std_logic。該位為1表示該月為30天