計(jì)算機(jī)科學(xué)與技術(shù)專(zhuān)業(yè)研討-全文預(yù)覽
【正文】 以分為任務(wù)級(jí)并行性、循環(huán)級(jí)并行性和指令級(jí)并行性三類(lèi)1，相應(yīng)地，在體系結(jié)構(gòu)上也發(fā)展了各種技術(shù)來(lái)利用這三類(lèi)不同的并行性，如針對(duì)任務(wù)級(jí)并行性的并行計(jì)算機(jī)(又分為共享存儲(chǔ)多處理機(jī)和消息傳遞多計(jì)算機(jī))，針對(duì)循環(huán)級(jí)并行性的流水線向量機(jī)，以及針對(duì)指令級(jí)并行性而在單個(gè)處理器的設(shè)計(jì)中采用的流水線、多發(fā)射、亂序執(zhí)行等技術(shù)?！娟P(guān)鍵字】指令級(jí)井行編譯ABSTRACTInstructionlevel parallel processing is the key technology to Promoting the performance of current processor，and piler Plays a very important role in it .In the past 20 years，a lot of work has been done in this area . But there are still problems remaining unresolved .This paper discusses in depth the key techniques of instructionlevel parallelizing piler design，including : design of intermediate representation , register allocation , global instruction scheduling，etc . We applied the results in the development of a prototype C piler for a VLIWlike processor ,and acquired fairly good effect.Present the multiview intermediate representation : we introduce the concept of view in the design of intermediate representation(IR).With multiple discretely defined views of a single object，we can satisfy the different requirements to IR of algorithms of different passes. We separate the physical view and logic view of IR，and make algorithms work on the highlevel logic view，and map the highlevel algorithms into lowlevel IR through view transformations. With this technique we can simplify the formulation of algorithms and reduce the development cost，Promote the abstract level and reusability.Keywords :Instruction一Level Parallelism(ILP)一、引言對(duì)于計(jì)算能力的日益增長(zhǎng)的需求推動(dòng)著計(jì)算技術(shù)的發(fā)展，促使計(jì)算系統(tǒng)的設(shè)計(jì)和制造者不斷發(fā)展并應(yīng)用各種新技術(shù)。近二十年來(lái)，指令級(jí)并行編譯一直是工業(yè)界和學(xué)術(shù)界關(guān)注的熱點(diǎn)，在這方面也已作了大量的工作，但許多問(wèn)題仍未得到圓滿解決。甘肅政法學(xué)院本科學(xué)年論文（設(shè)計(jì)） 題 目 ________指令級(jí)并行技術(shù)研究 計(jì)算機(jī)科學(xué)學(xué)院計(jì)算機(jī)科學(xué)與技術(shù)專(zhuān)業(yè)08級(jí)計(jì)本2班學(xué) 號(hào)：_ 200881010227__姓 名：_____祁云龍____ 指導(dǎo)教師：__ 王云峰__ 成 績(jī)：________________完成時(shí)間：__2011_年 __12_月 目錄一、引言 1 2 2 3（一）指令級(jí)并行體系結(jié)構(gòu)的分類(lèi) 3（二）各類(lèi)指令級(jí)并行體系結(jié)構(gòu)的特點(diǎn) 4 4 5（一） M一MACHINE體系結(jié)構(gòu) 5（二） MCC總體結(jié)構(gòu) 6參獻(xiàn) 88 / 10 指令級(jí)并行技術(shù)研究祁云龍【摘 要】指令級(jí)并行處理是提高處理器性能的關(guān)鍵，而編譯器在其中的作用是至關(guān)重要的。通過(guò)這種方法，可以簡(jiǎn)化算法表述，提高算法的抽象層次，從而達(dá)到降低開(kāi)發(fā)代價(jià)，提高算法可重用性的目的。特別是近二
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