【正文】 hers believe that this procedure more accurately model factory handling conditions than either the human body or the machine model. CDM testing produces very brief pulses of extremely high current.. A typical testing regimen will specify 1 to CDM testing. Effects Electrostatic discharge causes several different forms of electrical damage, including dielectric rupture, dielectric degradation, and avalancheinduced junction leakage. In extreme cases, ESD discharges can even vaporize metallization or shatter the bulk silicon. Less than 50V will rupture the gate dielectric of a typical MOS transistor. The rupture occurs in nanoseconds, requires little or no sustained current flow ,and is for all intents and purposes, irreversible. The rupture typically shorts the gate and the back gate of the damaged transistor. Capacitors that use thin insulating dielectrics are also vulnerable to this failure mechanism. An ESD discharge that strikes a pin connecting only to gates or capacitors will usually destroy these devices. If the pin also connects to diffusions, then these may avalanche before the gate oxide ruptures. The integrity of a dielectric can be promised by an ESD event that does not actually rupture it. The weakened dielectric can fail at any time, per haps after hundreds or thousands of hours of flawless the failure dose not occur until the product has been delivered to the customer. Testing cannot screen out this type of delayed ESD failure。 a typical value is 500. Each conductor layer is vulnerable to the antenna effect during etching and ash, so each layer has its own peripheral and areal antenna ratios. Consider the case of metal2. Near the end of the etch process, the individual metal2 geometries bee separated from one anther. However, these geometries may be connected together through lower conductor layers. Therefore, the antenna effect cannot be evaluated on a geometrybygeometry basis. Instead, one must define collections of electrically connected geometries called nodes. During the metal2 etch, each node collects charge proportional to the metal2 periphery exposed to the plasma and injects this charge through the active gate beneath poly geometries forming part of the node. Therefroe, the metal2 peripheral antenna ratio of a node equals the total metal2 periphery of the node divided by the active gate beneath the poly geometries of the node. Similarly, the evaluation of ash damage depends upon the metal2 areal antenna ratio, defined as the total metal2 area of a node divided by the active gate area beneath the poly geometries of the node. A great deal of effort has been expended to understand the relationship between antenna ratios and gate dielectric damage, but much remains uncertain. Some researchers have uncovered evidence that PMOS gate oxides are considerably more sensitive to plasmainduced damage than NMOS gate oxides. Other researchers have shown that oxide isolation greatly reduces plasmainduced damage, presumably by limiting the current that can flow through any given area of gate oxide. Preventative Measures Any node whose antenna ratio exceeds specifications must be reworked. The exact techniques employed depend upon which layer is involved. In the case of polysilicon, the ratio can be reduced by inserting metal jumpers. Consider the case shown in Figure. This circuit contains a very long poly lead that crosses a minimumsize MOS transistor M1. The antenna ratios of this poly geometry could clearly bee very large. If, however, a short metal jumper is inserted in the poly lead next to the transistor, then the single poly geometry now bees two separate geometries. The geometry on the left (connecting to the gate of transistor M1) has relatively small antenna ratios. The geometry on the right (connecting to the source/drain of transistor M2) has zero antenna ratios because no gate oxide lies beneath it. Therefore, the addition of the metal jumper has eliminated any potential problem. 1M1MoatNM Poly 1?Metal 2M2MNMo at o x i d e g a t e eV u l a n e r a b lj u m p e r 1M e t a l Figure 3 Metal layers are somewhat more difficult to evaluate because metal nodes can connect to diffusions that leak away the charge before it damages gate oxides. For processes that employ gate oxides thicker than about 400?, the source/drain junctions of the MOS transistors will typically avalanche before the gate oxides can be damaged. In such cases, any node that connects to a source/drain diffusion can generally be ignored when puting antenna ratios. If a metal node is found to have an excessive antenna ratio, the problem can be eliminated either by placing a jumper on a higher metal layer (as discussed previously in connection with poly), or by connecting a source/drain diffusion to the node. If the circuit dose not include a transistor connected to the node, then a small structure called a leaker can be attached instead. Figure show shows examples of NSD/Pepi leaker is preferred. This structure is essentially a diode whose anode is connected to the metal node and whose cathode is connected to the substrate. If the voltage on the node drops below the substrate potential, then the leaker will forwardbias and clamp the voltage. If the voltage on the node rises above substrate potential, then the NSD/Pepi junction will avalanche before the thick oxide is damaged. N M o a tC o n t a c twellN ?PM oatC o n t a c t Figure 4 Leakers for thinoxide processes are somewhat more problematic. The avalanche voltage of an NSD/Pepi junction cannot be relied upon to protect a gate oxide much thinner than 400?. Experience has shown that nodes in thinoxide processes can be protected by a bination of NSD/Pepi and PSD/Nwell leakers. The NSD/Pepi leaker will forwardb