【正文】 or by setting TCLK and/or RCLK in T2CON. Note that the baud rates for transmit and receive can be different if Timer 2 is used for the receiver or transmitter and Timer 1 is used for the other function. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode. The baud rate generator mode is similar to the autoreload mode, in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16bit value in registers RCAP2H and RCAP2L, which are preset by software. The baud rates in Modes 1 and 3 are determined by Timer 2’s overflow rate according to the following equation. Modes 1 and 3 Baud Rates= Tim e r 2 O v e rflo w R a te16 The Timer can be configured for either timer or counter operation. In most applications, it is configured for timer operation (CP/T2 =0). The timer operation is different for Timer 2 when it is used as a baud rate generator. Normally, as a timer, it increments every machine cycle (at 1/12 the oscillator frequency). As a baud rate generator, however, it increments every state time (at 1/2 the oscillator frequency). The baud rate formula is given below. ? ?M o d e s 1 a n d 3 O s c il l a to r F r e q u e n c yB a u d R a te 3 2 6 5 5 3 6 R C A P2 H, R C A P2 L? ?? Where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16bit unsigned integer. This figure is valid only if RCLK or TCLK=1 in T2CON. Note that a rollover in 6 TH2 does not set TF2 and will not generate an interrupt. Note too, that if EXEN2 is set, a 1to0 transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus, when Timer 2 is in use as a baud rate generator, T2EX can be used as an extra external interrupt. Note that when Timer 2 is running (TR2=1) as a timer in the baud rate generator mode, TH2 and TL2 should not be read from or written to. Under these conditions, the Timer is incremented every state time, and the results of a read or write may not be accurate. The RCAP2 registers may be read but should not be written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers. The AT89S52 has a total of six interrupt vectors: two external interrupts ( INT0 and INT1 ), three timer interrupts (Timers 0,1 and 2), and the serial port interrupt. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once. Note that bit position is unimplemented. User software should not write a 1 to this bit position, since it may be used in future AT89 products. Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and that bit will have to be cleared in software. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows. Characteristics XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be configured for use as an onchip oscillator. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a dividebytwo flipflop, but minimum and maximum voltage high and low time specifications must be observed. 7 AT89S52 單片機(jī)簡(jiǎn)介 VCC： 電源 GND： 接地 P0： P0 口是一個(gè) 8 位開路漏極 雙向 I/O 口。在這種模式下， P0 具有內(nèi)部上拉電阻。 P1 輸出緩沖器能驅(qū)動(dòng) 4 個(gè) TTL 輸入 。 在 Flash 編程和校驗(yàn)時(shí)， P1 口 也 接收低位地址字節(jié)。 用作輸入 時(shí)，被外部拉低的 P2 引腳由于內(nèi)部 上拉 電阻的原因，將輸出電流（ IIL）。在 Flash 編程和校驗(yàn)時(shí)， P2 口也接收高位地址字節(jié)和一些控制信號(hào)。 用作輸入 時(shí)，被外部拉低的 P3 引腳由于內(nèi)部 上拉 電阻的原因，將 輸出電流（ IIL）。 當(dāng)振蕩器重置設(shè)備 時(shí)， 引腳上的高電平作用 2 個(gè)機(jī)器工作周期 。 ALE/ PROG ： 地址鎖存 器選通 （ ALE）是訪問外部 存儲(chǔ)器時(shí)，鎖存低位地址的輸出脈沖 。如果需要， 通過設(shè)置 0 位或 SFR 定位 8EH， ALE 操作將無效。 PSEN ： 允許程序存儲(chǔ)器 （ PSEN ） 是外部程序存儲(chǔ)器的讀選通 。為了執(zhí)行內(nèi)部程序 ， EA 應(yīng)該接 VCC。 MCS51 設(shè)備 有單獨(dú)的 程序和數(shù)據(jù)存儲(chǔ)器 地址空間