外文翻譯--單片機at89c-全文預(yù)覽
【正文】 t Pin Alternate Functions RXD (serial input port) TXD (serial output port) INTO (external interrupt 0) INTO (external interrupt 1) T0 (timer 0 external input) T1 (timer 1 external input) WR (external data memory write strobe) RD (external data memory read strobe) RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives High for 96 oscillator periods after the Watchdog times DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO,the RESET HIGH out feature is enabled. 設(shè)計巴巴工作室 ALE/ PROG Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input ( PROG ) during Flash programming. In normal operation, ALE is emitted at a constant rate of1/6 the oscillator frequ ency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin isweakly pulled high. Setting the ALEdisable bit has no effect if the microco ntroller is in external execution mode. PSEN Program Store Enable ( PSEN ) is the read strobe to external program memory. When the AT89S52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. EA /VPP External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be ternally latched on reset. EA should be strapped to VCC for internal rogram pin also receives the 12volt programming enable voltage(VPP) during Flash programming. XTAL1 Input to the inverting oscillator amplifier and input to the nternal clock operating circuit. 設(shè)計巴巴工作室 XTAL2 Output from the inverting oscillator amplifier. Special Function Registers A map of the onchip memory area called the Special FunctionRegister (SFR) space is shown in Table that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write 1s to these unlisted locations,since they may be used in future products to invokenew features. In that case, the reset or nactive values of the new bits will always be 0.
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鄂ICP備17016276號-1