【正文】 uppose LVD is given to . When the voltage drops below , the b15 of Port_LVD_Ctrl is read as HIGH. In such state, program can be designed to react to this condition. Low voltage reset In addition to the LVD, the SPCE061A has another important function, Low Voltage Reset (LVR). With the LVR function, a reset signal is generated to reset system when the operating voltage drops below for 10 consecutive CPU clock LVR, the CPU bees unstable and malfunctions when the operating voltage drops below . The LVR will reset all functions to the initial operational (stable) states when the voltage drops below . 13 Interrupt The SPCE061A has 14 interrupt sources, grouped into two types, FIQ (Fast Interrupt Request) and IRQ (Interrupt request).The priority of FIQ is higher than IRQ. FIQ is the highpriority interrupt while IRQ is the lowpriority one. An IRQ can be interrupted by a FIQ, but not by another FIQ cannot be interrupted by any other interrupt sources. I/O Two I/O ports are built in SPCE061A, PortA and PortA is an ordinary I/O with programmable wakeup capability. In addition to the regular IO function, the PortB can also perform some special functions in certain pins. Suppose operating voltage is running at (VDD) and VDDIO (power for I/O) operates from (VDD) to . In such condition, the I/O pad is capable of operating from 0V through VDDIO. However IOB13 and IOB14 are remended to operate = during standby mode, otherwise these two IOs will have current leakage. The following diagram is an I/O schematic. Although data can be written into the same register through Port_Data and Port_Buffer, they can be read from different places, Buffer (R) and Data (R).The IOA [7:0] is the key wakeup port. To activate key wakeup function, latch data on PORT_IOA_Latch and enable the key wakeup function. Wakeup is triggered when the PortA state is different 14 from at the time latched. In addition to an ordinary I/O port, PortB carries some special functions. Timer / Counter The SPCE061A provides two 16bit timers/counters, TimerA and TimerB. The TimerA is called a universal is ageneralpurpose clock source of TimerA es from the bination of clock source A and clock source TimerB, the clock source is given from source timer overflows,an INT signal is sent to CPU to generate a timeout signal. Initially, write a value of N into a timer and select a desired clock source, timer will start counting from N, N+1, N+2, ... through FFFF. An INT (TimerA/TimerB) signal is generated at the next clock after reaching “ FFFF” and the INT signal is transmitted to INT controller for further the same time, N will be reloaded into timer and start all over clock source A is a high frequency source and clock source B is a low frequency bination of clock source A and B provides a variety of speeds to “ 1” represents pass signal and not contrast,“ 0” indicates deactivating EXT1 and EXT2 are the external clock ,counter can generate timeout signal for input clock source to a four bits (16 levels) PWM pulse width variety of clock duration can be generated and exported from IOB8 (APWMO) and IOB9 (BPWMO). The following example is a 3/16duration APWMO waveform is made by selecting a pulse width through Port_TimerA_Ctrl (W) [9:6].As a result,each 16 cycles will generate a pulse width defined in control PWM signals can be applied for controlling the speed of motor or other devices. Generally speaking,the clock source A and C are fast clock sources and source B es from RTC system(32768Hz).Therefore,clock source B can be utilized as a precise counter for time counting,.,the 2Hz clock can be used for real time counting. Timebase Timebase, generated by 32768Hz,is a bination of frequency selections. The outputs 15 of timebase block are named to TMB1 and is frequency for TimerA(Clock source B).The TMB1 and TMB2 are the sources for Interrupt(IRQ6).Furthermore, timebases generates additional 2Hz to 4096Hz interrupt sources (IRQ4 and IRQ5) for RealTimeClock (RTC). Sleep, Wakeup and Watchdog Wakeup and sleep 1) Sleep: After poweron reset,IC starts running until a sleep mand a sleep mand is accepted, IC will turn the system