【正文】 the LM1881 coincides with the leading edge of the first vertical serration, sixteen positive or negative transitions later will be the start of line 14 in either field. At this point simple counters can be used to select the desired line(s) for insertion or deletion of data. VIDEO LINE SELECTOR The circuit in Figure 3 puts out a singe video line according to the binary coded information applied to line select bits b0– b7. A line is selected by adding two to the desired line number, converting to a binary equivalent and applying the result to the line select inputs. The falling edge of the LM1881’s vertical pulse is used to load the appropriate number into the counters (MM74C193N) and to set a start count latch using two NAND gates. Composite sync transitions are counted using the borrow out of the desired number of counters. The final borrow out pulse is used to turn on the analog switch (CD4066BC) during the desired line. The falling edge of this signal also resets the start count latch,thereby terminating the counting. The circuit, as shown, will provide a single line output for each field in an interlaced video system (television) or a single line output in each frame for a noninterlaced video system (puter monitor). When a particular line in only one field of an interlaced video signal is desired, the odd/even field index output must be used instead of the vertical output pulse (invert the field index output to select the odd field). A single counter is needed for selecting lines 3 to 14。s in this graph is linear, meaning that a value as large as M? can be used for RSET (twice the value as the maximum at 30 181。s serration pulse spacing. A mon question is how can one calculate the required RSET with a video timing standard that has no serration pulses during the vertical blanking. If the default vertical sync is to be used this is a very easy task. Use the ―Vertical Default Sync Delay Time vsRSET‖ graph to select the necessary RSET to give the desired delay time for the vertical sync output signal. If a second pulse is undesirable, then check the ―Vertical Pulse Width vs RSET‖ graph to make sure the vertical output pulse will extend beyond the end of the input vertical sync period. In most systems the end of the vertical sync period may be very accurate. In this case the preferred design may be to start the vertical sync pulse at the end of the vertical sync period, similar to starting the vertical sync pulse after the first serration pulse. A VGA standard is to be used as an example to show how this is done. In this standard a horizontal line is 32 181。s serration pulse separation is about 550 k?. Going to the ―Vertical Pulse Width vs RSET‖ graph one can see that 550 k? gives a vertical pulse width of about 180 181。 both NTSC and PAL do meet this requirement (the serration pulse is the remainder of the period, 10% to 15% of the horizontal half line). Remember this pulse is a positive pulse at the integrator but negative in Figure 1. This graph shows how long it takes the integrator to charge its internal capacitor above V1 With RSET too large the charging current of the integrator will be too small to charge the capacitor above V1, thus there will be no vertical synch output pulse. As mentioned above, RSET also sets the frequency of the internal oscillator. If the oscillator runs too fast its eight cycles will be shorter than the vertical sync portion of the posite sync. Under this condition another vertical sync pulse can be generated on one of the later serration pulse after the divide by 8 circuit resets the R/S flipflop. The first graph also shows the minimum RSET necessary to prevent a double vertical pulse, assuming that the serration pulses last for only three full horizontal line periods (six serration pulses for NTSC). The actual pulse width of the vertical sync pulse is shown in the ―Vertical Pulse Width vs RSET‖ graph. Using NTSC as an example,lets see how these two graphs relate to each other. The Horizontal line is 64 181。 a vertical sync pulse。 posite sync including both horizontal and vertical scan timing information。 however, any subcarrier content in the signal will be attenuated by almost 18 dB, effectively taking it below the parator threshold. Filtering will also help if the source is contaminated with thermal noise. The output waveforms will bee delayed from between 40 ns to as much as 200 ns due to this filter. This much delay will not usually be significant but it does contribute to the sync delay produced by any additional signal processing. Since the original video may also undergo processing, the need for time delay correction will depend on the total system, not just the sync stripper. VERTICAL SYNC OUTPUT A vertical sync output is derived by internally integrating the posite sync waveform (Figure 2). To understand the generation of the vertical sync pulse, refer to the lower left hand section Figure2. Note that there are two parators in the section. One parator has an internally generated voltage reference called V1 going to one of its inputs. The other parator has an internally generated voltage reference called V2 going to one of its inputs. Both parators have a mon input at their noninverting input ing from the internal integrator. The internal integrator is used for integrating the posite sync signal.