【正文】 在某些情況下，可供使用的單片機(jī)并行 I/O 口不足 8 根，數(shù)據(jù)的并行輸出已不可能，此時可考慮串行輸出方法。在本設(shè)計(jì)中，使用的是并行的 LED 驅(qū)動電路。它的標(biāo)準(zhǔn)工作電壓 2—6V。它的靜態(tài)功耗極小。我用的是四位八段式數(shù)碼管，所以每個數(shù)碼顯示器被點(diǎn)亮?xí)r每個引腳所需的最大電流為 4mA4=16mA。西 安 工 業(yè) 學(xué) 院 畢 業(yè) 論 文 225 負(fù)載部分系統(tǒng)組成負(fù)載回路主要由隔離電路，驅(qū)動電路，無極性輸入，變壓器、晶閘管整流裝置和電動機(jī)—發(fā)電機(jī)組組成。α 的變化范圍為0≤α≤1。（1） 定寬調(diào)頻法 這種方法是保持 t1 不變，只改變 t2，這樣使周期 T（或頻率）也隨之改變。目前，在直流電動機(jī)的控制中，主要使用定頻調(diào)寬法。 功率場效應(yīng)管（metal oxide semiconductor field effect transistor，MOSFET）是一種載流子導(dǎo)電的單極型器件，它要求的柵極驅(qū)動電流很小，因此可看成是電壓控制型元件是電壓型驅(qū)動器件。用普通的 TTL 直接驅(qū)動功率場效應(yīng)管,驅(qū)動電壓還顯得低一些。西 安 工 業(yè) 學(xué) 院 畢 業(yè) 論 文 246 原理圖的設(shè)計(jì) Protel99 原理圖的設(shè)計(jì)（schematic） 原理圖編輯器實(shí)際上就是原理圖的設(shè)計(jì)系統(tǒng)，用戶可以在該平臺下對電路圖進(jìn)行編輯與設(shè)計(jì)各修改。進(jìn)入設(shè)計(jì)窗口后，可以在首先執(zhí)行 design(設(shè)計(jì))/Options(選項(xiàng))菜單下設(shè)置圖紙的風(fēng)格和大小尺寸等，具體參數(shù)設(shè)置如下：(1)、圖紙方向的設(shè)置。Border 選擇項(xiàng)用來設(shè)置邊框顏色，在選擇了此項(xiàng)時，系統(tǒng)會彈出顏色對話框，你只需選擇所需顏色后點(diǎn)擊 OK 鍵后即可。在點(diǎn)擊 Design/options 后，選擇 change system font 按鈕，則可彈出字體對話框，您可以進(jìn)行字體設(shè)置了。在設(shè)置好以上基本的內(nèi)容后，則對原理圖編輯平臺半截元件庫。對元件庫進(jìn)行裝載以后，可通過 place(放置)/part（元件）命令直接進(jìn)行元件的放置，也可以用工具條上的按鈕，打開所對應(yīng)的對話框進(jìn)行元件的放置。作完以上步驟以后，下一步則要對所設(shè)計(jì)的電路圖進(jìn)行檢查。multiple names on 是檢查同一個網(wǎng)絡(luò)上是否擁有多個不同名稱的網(wǎng)絡(luò)標(biāo)識。b、Options 選項(xiàng)框 create report file 設(shè)置列出全部 ERC 信息并產(chǎn)生一個文本報告。執(zhí)行 design/create list 命令，生成網(wǎng)絡(luò)報表。Protel99 被設(shè)計(jì)成為一個客戶/服務(wù)器應(yīng)用程序，它包含有數(shù)目眾多的服務(wù)器程序，原理圖設(shè)計(jì)服務(wù)器、網(wǎng)絡(luò)生成服務(wù)器、電路仿真服務(wù)器、PCB 設(shè)計(jì)服務(wù)器和自動布線服務(wù)器等等。Protel99 強(qiáng)大的功能，可以使設(shè)計(jì)者隨心所欲的設(shè)計(jì)各種電子電路，是一個非常實(shí)用的 CAD 軟件。同時，對于一個有著特殊要求的電路來講，手工布局將極大地體現(xiàn)出設(shè)計(jì)者的構(gòu)思和靈感。最后，根據(jù)電路的功能單元對電路的全部元件進(jìn)行布局。根據(jù)電路功能單元，對電路的全部元器件進(jìn)行布局時，要符合以下原則：(1) 按電路的流程安排各個功能電路單元的位置，使布局便于信號流通，并使信號盡可能保持方向一致。布局過程中，應(yīng)盡量將相關(guān)的元器件就近放置，以減少走線的長度；時鐘電路、晶振、電容應(yīng)緊貼相接的芯片，這樣有利于抗干擾，提高電路工作的可靠性。在整個布線過程中，應(yīng)遵循以下原則：1 輸入和輸出端的導(dǎo)線應(yīng)盡量避免相鄰平行。尤其是電源線和地線。對于集成電路，其間距最小可到 。這樣有利于排除銅箔與基板粘合劑受熱產(chǎn)生的揮發(fā)性氣體。高頻電路宜采用多點(diǎn)串聯(lián)接地，地線應(yīng)短而粗。 本設(shè)計(jì)的中心即設(shè)計(jì)一個含有特定功能的典型單片機(jī)系統(tǒng)。 *本系統(tǒng)在工作、參數(shù)設(shè)定的兩種模式下實(shí)現(xiàn)三鍵輸入（復(fù)用） 。ATMEL 公司把自身的先進(jìn) Flash 存儲器技術(shù)和 80C31 核相結(jié)合，生產(chǎn)出 Flash 單片機(jī) AT89C51 系列?；谝陨咸攸c(diǎn)，在需要 I/O 線不多的控制場合，選用它作為核心控制芯片，可使電路極大的簡化，而且程序的編寫及固化也相當(dāng)方便、靈活。在這里，我將采用型號為 SN75LBC176，它的標(biāo)準(zhǔn)驅(qū)動節(jié)點(diǎn)數(shù)為 32，采用半雙工通訊。此系統(tǒng)是工業(yè)控制計(jì)算機(jī)發(fā)出控制命令，通過與單片機(jī)的通信，按命令單片機(jī)產(chǎn)生控制步進(jìn)電機(jī)運(yùn)轉(zhuǎn)的脈沖信號。單片機(jī)負(fù)責(zé)從工業(yè)控制計(jì)算機(jī)上接收命令，并將其轉(zhuǎn)換成控制脈沖信號，從并行口發(fā)出到步進(jìn)電機(jī)驅(qū)動電路。*對所設(shè)計(jì)系統(tǒng)有一個初步的設(shè)計(jì)方案。第七周至第十二周: 初步完成具體的電路設(shè)計(jì),運(yùn)行通過。第十六周: 進(jìn)入畢業(yè)設(shè)計(jì)的后期工作,完善論文,準(zhǔn)備答辯。此項(xiàng)畢業(yè)設(shè)計(jì)囊括了專業(yè)電工、電子、電力電子技術(shù)，MCS—51 系列單片機(jī)工作原理及應(yīng)用技術(shù)， PROTEL 技術(shù)等學(xué)科知識。* X5043/45 接口芯片在該系統(tǒng)中，為解決電源開斷、瞬時電壓不穩(wěn)等不安全因素，將會造成系統(tǒng)死機(jī)、信息丟失、運(yùn)行不穩(wěn)定等故障，實(shí)現(xiàn)系統(tǒng)安全可靠、穩(wěn)定、實(shí)時運(yùn)行，故采用 X5045 芯片。在使用 RS—485 總線時，如果簡單地按常規(guī)方式設(shè)計(jì)電路，在實(shí)際工程中可能有通信數(shù)據(jù)收發(fā)的可靠性問題。并行驅(qū)動的結(jié)構(gòu)較為簡單，并且在單片機(jī)的選擇上，采用了 AT89C51，它有 32 條 I/O 口線，采用并行驅(qū)動方式，接口完全夠用。西 安 工 業(yè) 學(xué) 院 畢 業(yè) 論 文 348．3 相關(guān)外文資料翻譯Complete Model of E2PROM Memory Cell for Circuit SimulationAbstractE2PROM memory devices are widely used in embedded applications. For an efficient design flow, a correct modeling of these memory cells in every operation condition bees more and more important, especially due to power consumption limitations. Although E2PROM cells are being used for a long time, very few pact models have been developed. Here，we present a plete pact model based on an original procedure to calculate the floating gate potential in dc conditions, without the need of any capacitive coupling coefficient. This model is designed as a modular structure, so to simplify program/erase and reliability simulations. Program/erase and leakage currents are included by means of simple voltagecontrolled current sources implementing their analytical expression. It can be used to simulate memory cells both during read operation (dc conditions) and during program and erase (transient conditions) giving always very accurate results. We will show also that, provided good description of degradation mechanisms, the same model can be used also for reliability simulations, predicting charge loss due to tunnel oxide degradation.Index TermsCircuit simulation, puter aided design(CAD), integrated circuits, modeling, semiconductor memories.I. INTRODUCTIONIn the semiconductor industry, “modeling” and “characterization” have different meanings. Compact model means an analytic model of the electrical behavior of a circuit element, as used in a SPICElike circuit simulator, and characterization means the procedure by which the parameters of pact model are determined for devices in a particular integrated circuit (IC) manufacturing technology.Compact models should be formulated physically, as functions of both the fundamental process parameters that control device electrical behavior and geometric layout parameters associated with a device (both adjustable layout parameters, such as device length and width 西 安 工 業(yè) 學(xué) 院 畢 業(yè) 論 文 35and technologydependent layout parameters derived from design rules, such as spacing between active areas and implant areas, etc.). There are three main reasons for preferring physically based pact models [1]. First, they provide the best basis for statistical modeling[2]. Second, they provide the best basis for mismatch modeling. Third, during the life cycle of a manufacturing technology there are changes, both in process flow and in design rules, that require to quickly retarget the design library.Although the importance of E2PROM memory cells has grown, very few pact models have been developed to be used in SPACElike simulators [3] to study dc and transient behavior of plex circuits containing E2PROM cells. E2PROM cells are based on floating gate (FG) devices, which are metaloxidesemiconductor (MOS) transistors where a conductive layer is interleaved between gate and channel and it is surrounded by insulator. The conductive layer is called FG. These devices’ threshold voltage can be changed by injecting and/or extracting charge in/from the FG. Because of the lack of reliable pact models in the industry plex circuit