【正文】 和檢驗(yàn)， 因而被廣泛得到應(yīng)用，是一種重要的基帶傳輸碼型。傳輸碼型中應(yīng)含有定時(shí)時(shí)鐘信息，以利于 接 收端提取定時(shí)時(shí)鐘，在基帶傳輸系統(tǒng)中，定時(shí)信 息是在接收端 恢復(fù) 原始信息所必需的。數(shù)字基帶信號(hào)是數(shù)字信息的電脈沖表示，不同形式的數(shù)字基帶信號(hào)(又稱為碼型 )具有不同的頻譜結(jié)構(gòu)，合理地設(shè)計(jì)數(shù)字基帶信號(hào)以使數(shù)字信息變換為適合給定信道傳輸特性的頻譜結(jié)構(gòu)，是基帶傳輸首要考慮的問(wèn)題。 關(guān)鍵詞： HDB3 碼； FPGA； EDA； VHDL； 編譯碼器 ii Abstract HDB3 code is one of codes used in the transmission system. It has no DC ponents and a few of LF ponents. Moreover, it has continuous zeros no more than three. The features of HDB3 code help the signal to be rebuilt and be checked for error easily, so HDB3 code is the monly used code in the transmission system. Low cost, dependability, short design cycle and repeated programmability are the features of FPGA. You can design hardware of digital circuits by using software as a result of using FPGA with EDA. It will construct the digital system quickly and reduce the cost of design. This paper first introduces the development and background of HDB3, FPGA and EDA, and then expands VHDL, which is monly used as a designentry language for EDA. A summary of digital circuits? design by using VHDL is provided. Moreover, the principle and features of HDB3 code is introduced. According to principle of HDB3 codes, the encoder and decoder is designed by using VHDL. Finally, the plan of design, the flow of software design and the simulated waveform of HDB3 encoder and decoder is presented, showing correctness of the design. Keywords: HDB3 code； FPGA； EDA； VHDL； Encoder and Decoder iii 目 錄 摘 要 ....................................................................................................................................................................I ABSTRACT ............................................................................................................................................................ II 第一章 前言 .............................................................................................................................................................1 HDB3碼的簡(jiǎn)述 ...................................................................................................... 1 FPGA 的簡(jiǎn)介 ......................................................................................................... 2 概述 ..................................................................................................................................2 FPGA基本 結(jié)構(gòu)及特點(diǎn) ..................................................................................................2 EDA技術(shù) ............................................................................................................... 4 VHDL 硬件描述語(yǔ)言 ............................................................................................... 4 VHDL 簡(jiǎn)介 ......................................................................................................................4 VHDL 的優(yōu)點(diǎn) ..................................................................................................................5 VHDL 設(shè)計(jì)硬件電路的方法 .........................................................................................6 第二章 HDB3 碼的編譯規(guī)則 ................................................................................................................................9 ............................................................................................. 9 HDB3碼的編碼規(guī)則 ............................................................................................... 9 HDB3碼的譯碼規(guī)則 ..............................................................................................10 HDB3碼的檢錯(cuò)能力 ..............................................................................................10 第三章 HDB3 編碼器的 FPGA實(shí)現(xiàn) ................................................................................................................11 編碼器實(shí)現(xiàn)分析 ................................................................................................... 11 HDB3編碼器的設(shè)計(jì)思 路 ....................................................................................... 11 4 連‘ 0’的檢出加 V 及判 ?1?極性 ...........................................................................11 取代節(jié)選取 ....................................................................................................................11 設(shè)計(jì)建模 .............................................................................................................12 4 連 0 的檢出， AMI 編碼及插 V.............................................................................. 13 補(bǔ) B................................................................................................................................ 14 軟件仿真 .............................................................................................................15 第四章 HDB3譯碼器的 FPGA 實(shí)現(xiàn) ..................................................................................................................... 16 譯碼器的實(shí)現(xiàn)分析 ...............................................................................................16 HDB3編碼器的設(shè)計(jì)思路 .......................................................................................16 V 的檢測(cè) ........................................................................................................................ 16 扣 V 扣 B ........................................................................................................................ 16 iv 設(shè)計(jì)建模 .............................................................................................................17 V 碼、誤碼 檢測(cè) .....