【正文】 ystem verilog 自動(dòng)對比平臺的搭建，基于 c語言的對比模型，完成自動(dòng)對比，加速驗(yàn)證的速度。 Out of order execution and advanced Cache design technology to improve the efficiency of the pipeline. The processor has three implementation ponents and a memory ponent is fully patible with the MIPS III fixed, floatingpoint instruction set system. This article is divided into the following sections. 1) Processor architecture memory access and issue module design The processor architecture is a key part of the impact the work efficiency of the entire processor, the only reasonable structure to the efficiency of the processor to the highest. RSIC processor briefly works as a whole on the basis of detailed specific design of the issue module and the memory access ponents. 2) The processor delay debugging The operation speed of the processor is the most important criteria to measure the processor is good or bad, while closely related to the puting speed and processor frequency. This article describes mon of several ASIC delay testing method, specific work delayed the missioning process by the transmitter module. 3) Based on the VMM verification methodology microprocessor verification In this paper, Auto Contrast platform based on the systemverilog structures, based on the parison model of the c language, plete auto contrast, accelerate the validation speed. Division of the channel based on functional coverage, based on the embedded assembler directed test preparation. Ensure the functional correctness of the entire microprocessor. Key words ： Microprocessor architecture， Memory access， Delay debugging ，西安理工大學(xué)碩士學(xué)位論文 IV Functional coverage verification 目錄 V 目錄 1 緒論 .................................................................................................................................................. 1 ...................................................................................................................... 1 ...................................................................................................................... 1 ...................................................................................................................... 2 .......................................................................................................................... 3 2． 64bit MIPS架構(gòu)處理器體系結(jié)構(gòu) .................................................................................................... 4 RSIC CPU簡介 ....................................................................................................................... 4 ............................................................................................................................ 4 （ pipeline）設(shè)計(jì)思想 ................................................................................................. 6 ............................................................................................................ 7 后繼指令等待 ............................................................................................. 7 流水線空 泡 ........................................................................................................ 7 后繼指令等待 ............................................................................................. 7 64bit MIPS架構(gòu)處理器模塊設(shè)計(jì) .............................................................................................. 8 ..................................................................................................................... 8 ..................................................................................................... 9 .............................................................................................................. 10 ...............................................................................................................11 ..............................................................................................11 ................................................................................................. 13 ........................................................................................................ 15 SRAM使用簡介 ........................................................................................................... 16 dcache存取數(shù)據(jù)維護(hù) .................................................................................................... 18 ........................................................................................................... 19 ............................................................................................................................... 20 IQ（指令隊(duì)列）維護(hù) .................................................................................................. 20 ............................................................................................................. 22 ............................................................................................................. 23 ........................................................................................................................ 24 4 基于 64bit MIPS架構(gòu)處理器整體結(jié)構(gòu)延遲調(diào)試 ............................................................................. 25 ............................................................................................................................ 25 ....................................................................................................... 25 ........................................................................................................ 26 .................................................................................................... 27 .......................................................................................... 29 5 基于 64bit MIPS架構(gòu)處理器整體結(jié)構(gòu)功能覆蓋率驗(yàn)證 .................................................................... 31 vmm驗(yàn)證方