【正文】 摘要 I 分類號(hào) UDC 密 級(jí) 學(xué) 號(hào) 0809090560 碩士學(xué)位論文 微處理器訪存部件設(shè)計(jì)及結(jié)構(gòu)功能驗(yàn)證 學(xué) 科 名 稱： 微電子學(xué)與固體電子學(xué) 微處理器訪存部件設(shè)計(jì)及結(jié)構(gòu)功能驗(yàn)證 陳俊瑩 西安理工大學(xué) 西安理工大學(xué)碩士學(xué)位論文 II 論文題目： 微處理器訪存部件設(shè)計(jì)及結(jié)構(gòu)功能驗(yàn)證 學(xué)科 名稱 ：微電子學(xué)與固體電子學(xué) 摘 要 高性能的微處理器設(shè)計(jì)是整個(gè)信息技術(shù)和計(jì)算機(jī)應(yīng)用市場(chǎng)競(jìng)爭(zhēng)的重要焦點(diǎn)和關(guān)鍵內(nèi)容，因此設(shè)計(jì)高效的微處理器結(jié)構(gòu)具有重大的意義。 本文主要研究 RSIC 處理 器的結(jié)構(gòu)設(shè)計(jì)， 它是一個(gè)通用 64位 RISC 結(jié)構(gòu)，四發(fā)射的超標(biāo)量和超流水線微處理器，采用亂序執(zhí)行和先進(jìn)的 Cache 設(shè)計(jì)等技術(shù)提高流水線的效率。處理器有三個(gè)執(zhí)行部件和一個(gè)訪存部件。完全兼容 MIPSⅢ定、浮點(diǎn)指令集系統(tǒng)。本文主要分為以下幾個(gè)部分： 1）處理器發(fā)射模塊和訪存模塊設(shè)計(jì) 處理器的結(jié)構(gòu)是影響整個(gè)處理器的工作效率的關(guān)鍵部分，只有合理的結(jié)構(gòu)才能使處理器的效率達(dá)到最高。本文在簡(jiǎn)述整個(gè) RSIC 處理器的整體工作原理的基礎(chǔ)上詳細(xì)介紹了發(fā)射模塊和訪存部件的具體設(shè)計(jì)。 2）處理器延遲調(diào)試 處理器的運(yùn)算速度是衡量處理 器好壞的最重要的標(biāo)準(zhǔn)，而運(yùn)算速度和處理器的頻率息息相關(guān)。本文介紹了通用的幾種 ASIC 延遲調(diào)試方法，具體介紹了在工作中出現(xiàn)的發(fā)射模塊延遲的調(diào)試過程。 3） 基于 VMM 驗(yàn)證方法學(xué)的對(duì)微處理器的驗(yàn)證 本文通過基于 system verilog 自動(dòng)對(duì)比平臺(tái)的搭建，基于 c語言的對(duì)比模型，完成自動(dòng)對(duì)比，加速驗(yàn)證的速度?；诠δ芨采w率的通道劃分，基于嵌入式匯編的定向測(cè)試編寫。保證整個(gè)微處理器的功能正確性。 關(guān)鍵字： 微處理器結(jié)構(gòu)，訪存，延遲調(diào)試，功能覆蓋率驗(yàn)證 TITLE: microprocessor memory access ponent design and structure functional verification 摘要 III Major： Microelectronics and Solid Electronics Name： junying CHEN Signature: Supervisor： Prof. ningmei YU Signature: Abstract The highperformance microprocessor design is an important focus and key elements of the entire IT and puter application market petition to design efficient microprocessor architectures is of great significance. This paper mainly studies the structural design of the RSIC processor, it is a generalpurpose 64bit RISC architecture, four launch superscalar and superpipelined microprocessor。 Out of order execution and advanced Cache design technology to improve the efficiency of the pipeline. The processor has three implementation ponents and a memory ponent is fully patible with the MIPS III fixed, floatingpoint instruction set system. This article is divided into the following sections. 1) Processor architecture memory access and issue module design The processor architecture is a key part of the impact the work efficiency of the entire processor, the only reasonable structure to the efficiency of the processor to the highest. RSIC processor briefly works as a whole on the basis of detailed specific design of the issue module and the memory access ponents. 2) The processor delay debugging The operation speed of the processor is the most important criteria to measure the processor is good or bad, while closely related to the puting speed and processor frequency. This article describes mon of several ASIC delay testing method, specific work delayed the missioning process by the transmitter module. 3) Based on the VMM verification methodology microprocessor verification In this paper, Auto Contrast platform based on the systemverilog structures, based on the parison model of the c language, plete auto contrast, accelerate the validation speed. Division of the channel based on functional coverage, based on the embedded assembler directed test preparation. Ensure the functional correctness of the entire microprocessor. Key words ： Microprocessor architecture， Memory access， Delay debugging ，西安理工大學(xué)碩士學(xué)位論文 IV Functional coverage verification 目錄 V 目錄 1 緒論 .................................................................................................................................................. 1 ...................................................................................................................... 1 ...................................................................................................................... 1 ...................................................................................................................... 2 .......................................................................................................................... 3 2． 64bit MIPS架構(gòu)處理器體系結(jié)構(gòu) .................................................................................................... 4 RSIC CPU簡(jiǎn)介 ....................................................................................................................... 4 ............................................................................................................................ 4 （ pipeline）設(shè)計(jì)思想 ................................................................................................. 6 ............................................................................................................ 7 后繼指令等待 ............................................................................................. 7 流水線空 泡 ........................................................................................................ 7 后繼指令等待 ............................................................................................. 7 64bit MIPS架構(gòu)處理器模塊設(shè)計(jì) .............................................................................................. 8 ..................................................................................................................... 8 ..................................................................................................... 9 .............................................................................................................. 10 ...............................................................................................................11 ..............................................................................................11 ................................................................................................. 13 ........................................................................................................ 15 SRAM使用簡(jiǎn)介 ............................