【正文】 10倍，并降低了大約只有 10％的最終填筑質(zhì)量。如表 1： 最后，它表明在 [12， 13]，這是可取的 Raccept保證作為近似 值。而這些 “本地交換 “往往導(dǎo)致安置成本相對(duì)較小的變 化，越來越多被接受的可能性增加。當(dāng)溫度高于平均凈成本的一個(gè)單位時(shí)，它是不可能接受任何成本增 5 加的調(diào)配結(jié)果的，所以我們終止了退火。對(duì)使用路由資源成本的函數(shù)，其對(duì)資源的任何過度使用都會(huì)讓當(dāng)前路由發(fā)生事先迭代。一個(gè)重要的執(zhí)行細(xì)節(jié)值得一提。波前的迷宮路由被清空，新波前擴(kuò)展是從整個(gè)網(wǎng)絡(luò)布線開始發(fā)出的。因此，后者調(diào)用迷宮路由器的路由部分作為凈源會(huì)非常大，它將需要相當(dāng)長的時(shí)間以擴(kuò)大迷宮路由器波前部分到下一個(gè)接收器。由于增加新的路徑路由的部分有一個(gè)零成本，由于這項(xiàng)新路徑通常相當(dāng)小迷宮路由器將首先擴(kuò)大它范圍，也需要相對(duì)較少的時(shí)間來添加此新波，如果整個(gè)波前擴(kuò)展了能實(shí)現(xiàn)那么下一個(gè)接收器 6 將達(dá)到的速度遠(yuǎn)遠(yuǎn)超過現(xiàn)在。時(shí)鐘網(wǎng)和時(shí)序電路沒有遞交，因?yàn)樗ǔＪ锹酚赏ㄟ^專用 FPGA的商業(yè)網(wǎng)絡(luò)中的路由。 Doglegs 以往大多數(shù) FPGA布線結(jié)果認(rèn)為 “輸入引腳 doglegs”是可能。另外，通常有一個(gè)緩沖軌道之間的連接塊和它連接多路復(fù) 用這樣做的目的是為了提高速度，同時(shí)這也意味著緩沖輸入引腳 doglegs 不能被使用。列出三兩步（全球和詳細(xì)）路由與其它路由器進(jìn)行合并后的全球和詳細(xì)的路由。執(zhí)行安置和全局路 7 由，在試圖改善繞線同時(shí)需要超過 87％以上 VPR總資源數(shù)目。當(dāng)然這些工具都支持允許布局和布線的電路，對(duì)于 SPLACE / SROUTE組合 VPR還需要少 29％資源數(shù)目。我們使用 Flowmap [28]以技術(shù)圖每 4個(gè) LUT和拖動(dòng)塊并為 VPACK tobine 拖動(dòng)塊，進(jìn)入我們的基本邏輯電路塊 LUT。表 5還給出了大小每個(gè)邏輯塊的數(shù)量計(jì)算電路。顯然，世嘉處理無法進(jìn)行。而不是 1美元），由他們來處理如果減少需要跟蹤的總數(shù)。建立專門用于描述精密學(xué)術(shù)的 FPGA布局布線工具。在不久的將來 VPR將支持緩沖和分段路由結(jié)構(gòu)，我們計(jì)劃增加定時(shí)分析儀和時(shí)序驅(qū)動(dòng)的路由。maximum FPGA dimension. This results in Dlimit being the size of the entire chip for the first part of the anneal， shrinking gradually during the middle stages of the anneal， and being 1 for the lowtemperature part of the ， the anneal is terminated when T * Cost / Ns. The movement of a logic block will always affect at least one . When the temperature is less than a small fraction of the average cost of a ， it is unlikely that any move that results in a cost increase will be accepted， so we terminate the anneal. 3 Routing Algorithm VPR’s router is based on the Pathfinder negotiated congestion algorithm [14， 8].Basically， this algorithm initially routes each by the shortest path it can find，regardless of any overuse of wiring segments or logic block pins that may result. One iteration of the router consists of sequentially rippingup and rerouting (by the lowest cost path found) every in the circuit. The cost of using a routing resource is a function of the current overuse of that resource and any overuse that occurred in prior routing iterations. By 16 gradually increasing the cost of oversubscribed routing resources， the algorithm forces s with alternative routes to avoid using oversubscribed resources， leaving only the that most needs a given resource the experimental results in this paper we set the maximum number of router iterations to 45。 sign could not be successfully routed because SEGA ran out of SEGA to perform detailed routing on a global route generated by VPR increases the total number of tracks required to route the circuits by over 68% vs. having VPR perform the routing pletely. Clearly SEGA has difficulty routing large circuits when input pin doglegs are not encourage other FPGA researchers to publish routing results using these larger benchmarks， we issue the following “FPGA challenge.” Each time verified results which beat the previously best verified results on these benchmarks are announced， we will pay the authors $1 (sorry， $1 Cdn.， not $1 .) for each track by which they reduce the total number of tracks required from that of the previously best results. The 20 technologymapped lists， the placements generated by VPR and the currently best routing track total are available at 6 Conclusions and Future Work We have presented a new FPGA placement and routing tool that outperforms all such tools to which we can make direct parisons. In addition we have presented benchmark results on much larger circuits than have typically been used to characterize academic FPGA place and route tools. We hope the next generation of FPGA CAD tools will be pared on the basis of these larger benchmarks， as they are a closer approximation of the kind of problems being mapped into today’s of the main design goals for VPR was to keep the tool flexible enough to allow its use in many FPGA architectural studies. We are currently working on several improvements to VPR to further increase its utility in FPGA architecture research. In the near future VPR will support buffered and segmented routing structures， and soon after that we plan to add a timing analyzer and timingdriven routing. 21 References [1] S. Brown， R. Francis， J. Rose， and Z. Vranesic， FieldProgrammable Gate Arrays， Kluwer Academic Publishers， 1992. [2] Xilinx Inc.， The Programmable Logic Data Book， 1994. [3] AT amp。 just continue expanding normally. Since the new path added to the partial routing has a cost of zero， the maze router will expand around it at this new path is typically fairly small， it will take relatively little time to add this new wavefront， and the next sink will be reached much more quickly than if the entire wavefront expansion had been started from scratch. Figure 3 illustrates the difference graphically. 5 Experimental Results The various FPGA parameters used in this section were always chosen to allow a direct parison with previously published results. All the results in this section were obtained with a logic block consisting of a 4input LUT plus a flip flop， as shown in Figure 2. The clock was not routed in sequential circuits， as it is usually routed via a dedicated routing work in mercial FPGAs. Each LUT input appears on one side of the logic block， while the logic block output is accessible from both the bottom and right sides， as shown in Figure 4. Each logic block input or output can connect to any track in the adjacent channel(s) (. Fc = W). Each wire segment can connect to three other wiring segments at channel intersections ( Fs = 3) and the switch box topology is “disjoint” that is， a wiring segment in track 0 connects only to other wiring segments in track 0 and so on. Experimental Results with Input Pin Doglegs 18 Most previous FPGA routing results have assumed that “input pin doglegs” are possible