【正文】 I 摘 要 Turbo 碼將卷積碼和隨機交織器結合在一起，巧妙地實現了隨機編碼的思想，同時采用軟輸出迭代譯碼來逼近最大似然譯碼。 Turbo 碼已經在實際的通信系統(tǒng)中得到應用，但是隨著通信技術的發(fā)展和人們對通信業(yè)務需求的不斷提高，對 Turbo 碼的編譯碼技術進行研究很有必要。 通用異步收發(fā)器 (Universal Asynchronous Receiver Transmitter， UART)是一種能同時支持短距離和長距離數據傳輸的串行通信接口，被廣泛應用于微機和外設之間的數據交換。像 825 NS8250、 NSl6550 等都是常用的 UART 芯片，但是這些專用的串行接口芯片的缺點是數據傳輸速率比較慢，難以滿足高速率數據傳輸的場合，而更重要的就是它們都具有不可移植性，因此要利用這些芯片來實現 PC 機和 FPGA 芯片之間的通信，勢必會增加接口連線的復雜程度以及降低整個系統(tǒng)的穩(wěn)定性和有效性。 本課題就是針對 UART 的特點以及 FPGA 設計具有可移植性的優(yōu)勢，提出了一種基于 FPGA 芯片的嵌入式 UART設計方法，其中主要包括狀態(tài)機的描述形式以及自頂向下的設計方法，利用硬件描述語言來編制 UART 的各個子功能模塊以及頂層模塊，之后將其集成到 FPGA 芯片的內部，這樣不僅能解決傳統(tǒng) UART 芯片的缺點而且同時也使整個系統(tǒng)變得更加具有緊湊性以及可靠性。 本課題主要設計有波特率發(fā)生器模塊，接收啟動模塊， 接收模塊與發(fā)送模塊。在具體的設計過程中，利用利用 VHDL 語言對各個模塊進行編程，并通過 Modelsim 進行仿真測試。 關鍵詞 ： Turbo 碼 ； SOVA 算法 ； VHDL； Modelsim II Abstact Turbo code convolution code and randomly intertwined together, cleverly realized，random coding idea, at the same time soft output of iterative decoding is used to approximate maximum likelihood decoding. Turbo code has been applied in the actual munication system, but with the development of munication technology and the increasing demand for munication service people, study of Turbo code piled code technology is necessary. Universal Asynchronous transceiver (Universal Asynchronous Receiver Transmitter, UART) is a kind of can support both short and long distance data transmission in serial munication interface, is widely used in the data exchange between puter and peripherals. Like 8251, NS8250, NSl6550 are mon UART chip, but the dedicated serial interface chip disadvantage is that the data transmission speed is slow, difficult to meet the high speed data transmission occasions, but more important is that they are not portable, so to use these chips to realize munication between PC and FPGA chip, is bound to increase the plexity of the interface connections and reduce the stability and efficiency of the whole system. This topic is according to the characteristics of UART and the FPGA design with the advantages of portability, put forward a kind of embedded UART design method based on the FPGA chip, which mainly includes the description of the state machine form as well as the topdown design method, hardware description language was used to prepare the UART of each function module as well as the toplevel module, after the internal integrated into FPGA chips, such not only can solve the traditional UART chip faults and at the same time also bee more pact and the whole system reliability. This topic main design baud rate generator module, receives the start module, receiving module and sending module. In the detailed design process, with each module using verilog language programming, and through the Modelsim simulation test. Key Words： Turbo codes； SOVA algorithm； VHDL； Modelsim III 目錄 1 緒論 .............................................................................................................................. 1 Turbo 碼編譯碼器的研究目的和意義 ............................................................. 1 國內外研究現狀 ............................................................................................... 2 論文的安排 ....................................................................................................... 5 2 Turbo 碼編譯碼器的原理及算法 ................................................................................ 6 Turbo 碼編碼原理 ............................................................................................. 6 交織器 ............................................................................................................... 7 規(guī)則交織器 ............................................................................................ 7 偽隨機交織器 ........................................................................................ 8 系統(tǒng)卷積碼編碼器 ......................................................................................... 10 Turbo 碼譯碼原理 ........................................................................................... 11 SISO 譯碼模塊 ..................................................................................... 11 軟判決譯碼與硬判決譯碼 .................................................................. 12 譯碼器結構 .......................................................................................... 12 SOVA 譯碼算法 ............................................................................................. 13 累積路徑度量的計算 .......................................................................... 13 計算軟判決 值 ...................................................................................... 14 軟判決值的更新 .................................................................................. 14 外部信息值 的計算 .............................................................................. 14 改進的 SOVA 譯碼算法 ..................................................................... 14 3 編碼器的設計與實現 ................................................................................................ 17 偽隨機序列發(fā)生器 ......................................................................................... 17 交織器 ............................................................................................................. 17 分量編碼器模塊 ............................................................................................. 32 截余模塊 ......................................................................................................... 35 幀同步機 ......................................................................................................... 35 信道模型 ......................................................................................................... 36 接收機的分接插入模塊 ................................................................................. 37 IV 4 譯碼器的設計與實現 ......................