【正文】 理工大學(xué)學(xué)士學(xué)位論文 I 基于 ModelSim 的 FFT 算法的設(shè)計(jì)學(xué)士學(xué)位論文 理工大學(xué)學(xué)士學(xué)位論文 II 摘 要 快速傅立葉變換 (FFT)作為時(shí)域和頻域轉(zhuǎn)換的基本運(yùn)算，是數(shù)字譜分析的必要前提。傳統(tǒng)的 FFT 使用軟件或 DSP 實(shí)現(xiàn)，高速處理時(shí)實(shí)時(shí)性較難滿足，因此專用集成電路(ASIC)和可編程邏輯器件 (以現(xiàn)場(chǎng)可編程門陣列 FPGA 為代表 )應(yīng)運(yùn)而生。速度上 ASIC更占優(yōu)勢(shì)，但是隨著點(diǎn)數(shù)的增加，芯片面積將迅速擴(kuò)大，也就意味著成本的提高。而FPGA 內(nèi)部含有硬件乘法器，大量的存儲(chǔ)單元和可編程 I/O，十分適合于 FFT 處理器的實(shí)現(xiàn)，而且相對(duì) ASIC，成本低廉，可以反復(fù)編程，便于 調(diào)試，也更具市場(chǎng)競(jìng)爭(zhēng)力。 本文應(yīng)用 Verilog 語言完成 32 點(diǎn)基 2 復(fù)數(shù)的 FFT 處理系統(tǒng)設(shè)計(jì)，包括蝶形運(yùn)算單元設(shè)計(jì)、存儲(chǔ)單元設(shè)計(jì)、塊浮點(diǎn)單元設(shè)計(jì)、地址產(chǎn)生單元設(shè)計(jì)、功能切換單元設(shè)計(jì)以及時(shí)序控制單元的設(shè)計(jì)工作。以選取的 FPGA 器件庫為基礎(chǔ)，使用 modelsim 軟件進(jìn)行仿真，并對(duì)結(jié)果進(jìn)行分析。 關(guān)鍵詞：快速傅立葉變換； Verilog；單元設(shè)計(jì)； modelsim 仿真 理工大學(xué)學(xué)士學(xué)位論文 II Abstract Fast Fourier Transform is a necessary precondition of digital spectral analysis as the basic puting between the time domain and frequency domain. The traditional FFT uses software or DSP to realize, which is difficult to meet realtime in high speed processing. Application specific integrated circuit (ASIC) and programmable logic device (represented by field programmable gate array, FPGA) arises at the historic moment. ASIC has the advantage in the speed, but the chip area will expand rapidly with the processing points increasing, which means the improvement of costs. While FPGA contains hardware multipliers, massive memory cells and programmable I/O, so it is very suitable for implementation of FFT processor. Therefore, FPGA is lowcost, easy to debug and can be repeatedly programmed. It has more market petitiveness. Use Verilog language pleted 32 points 2 plex FFT processing system design, Including butterfly puting unit design, storage unit design, block floatingpoint unit design, the address generation unit design, the function switch unit design and timing control unit design work . On the basis of the selected library as the FPGA device, use the modelsim simulation software, and analyze the results. Key Words:FFT。Verilog。Unit design。modelsim simulation理工大學(xué)學(xué)士學(xué)位論文 III 目 錄 1 緒論 ................................................................... 1 課題的背景及意義 ...................................................................................................... 1 FFT 的國內(nèi)外發(fā)展研究現(xiàn)狀 ....................................................................................... 2 通用數(shù)字信號(hào)處理芯片 .................................................................................... 2 專用集成電路芯片 ASIC .................................................................................. 3 可編程邏輯器件 ................................................................................................ 3 篇章結(jié)構(gòu) ...................................................................................................................... 5 2 離散福利葉變換的快速算法的基本理論 ..................................... 6 基 2FFT 算法 ............................................................................................................... 6 定點(diǎn)數(shù)的相關(guān)概念 .................................................................................................... 15 定點(diǎn)數(shù)的定義 ................................................................................................. 15 定點(diǎn)數(shù)加減法的溢出及檢測(cè)方法 ................................................................. 15 定點(diǎn)數(shù)的定標(biāo) ............................................................................................................ 16 有限字長(zhǎng)效應(yīng) ............................................................................................................ 16 塊浮點(diǎn)數(shù) .................................................................................................................... 17 3 FFT 的算法設(shè)計(jì) ......................................................... 18 FFT 處理器的實(shí)現(xiàn)框圖 ............................................................................................. 18 蝶形運(yùn)算單元的設(shè)計(jì) ................................................................................................ 18 流水線結(jié)構(gòu) ................................................................................................................ 25 存儲(chǔ)單元的設(shè)計(jì) ........................................................................................................ 26 FFT 數(shù)據(jù)存取規(guī)律分析 .................................................................................. 26 雙口 RAM 及其地址發(fā)生器的設(shè)計(jì) .............................................................. 27 ROM 及其地址發(fā)生器的設(shè)計(jì) ....................................................................... 30 浮點(diǎn)單元的 設(shè)計(jì) ........................................................................................................ 33 時(shí)序控制單元的設(shè)計(jì) ................................................................................................ 38 4 基于 verilog 語言的 FFT 的設(shè)計(jì)與仿真 ..................................... 40 ModelSim 介紹 ........................................................................................................... 40 ModelSim 仿真 ........................................................................................................... 40 建立工程 .......................................................................................................... 41 理工大學(xué)學(xué)士學(xué)位論文 IV 加載文件 .......................................................................................................... 41 開始仿真 .......................................................................................................... 42 結(jié)果分析 .................................................................................................................... 44 結(jié) 論 ................................................................... 46 致 謝 ................................................................... 47 參考文獻(xiàn) ................................................................ 48 附錄 A 英文原文 ........................................................ 50 附錄 B 漢語翻譯 ........................................................ 55 理工大學(xué)學(xué)士學(xué)位論文 1 1 緒論 課題的背景及意義 隨著數(shù)字技術(shù)與計(jì)算機(jī)技術(shù)的發(fā)展，數(shù)字信號(hào)處理（ Digital Signal Processing， DSP）技術(shù)已深入