基于fpga的數(shù)字通信實(shí)現(xiàn)多路數(shù)據(jù)時(shí)分復(fù)用和解復(fù)用系統(tǒng)系統(tǒng)(已修改)
2025-06-19 08:13 本頁面
【正文】 第 1 頁 共 63 頁 ____________________________________________________________________________________________________ 摘 要 本設(shè)計(jì)實(shí)現(xiàn)多路數(shù)據(jù)時(shí)分復(fù)用和解復(fù)用系統(tǒng)。設(shè)計(jì)分為發(fā)端和收端，以 FPGA 作為主控核心。發(fā)端系統(tǒng)有三路并行數(shù)據(jù)輸入： A/D 轉(zhuǎn)換數(shù)據(jù)，撥碼開關(guān) 1 路和撥碼開關(guān) 2 路。這三路數(shù)據(jù)在 FPGA 的控制下作為串行碼分時(shí)輸出。發(fā)端 FPGA 包括分頻模塊、復(fù)用模塊和電壓顯示模塊。在收端，串行數(shù)據(jù)進(jìn)入 FPGA，并由FPGA 提取位時(shí)鐘，識(shí)別幀同步并解復(fù)用發(fā)端打包的三路碼。收端的 FPGA 包括數(shù)字鎖相環(huán)模塊、解復(fù)用模塊和電壓顯示模塊。發(fā)端 FPGA 輸入有三路 8bit 數(shù)據(jù)：第一路為 A/D 數(shù)據(jù)、第二路和第三路是撥碼開關(guān)產(chǎn)生的數(shù)據(jù)，另外 插入一路巴克碼。這四路碼組成一幀，由 FPGA 對(duì)其時(shí)分復(fù)用。 A/D 輸入端的模擬信號(hào)的電壓值通過 FPGA 處理，顯示在數(shù)碼管上。在收端， FPGA 首先提取位同步，然后識(shí)別幀同步，一旦識(shí)別出幀同步，F(xiàn)PGA 分別解復(fù)用三路數(shù)據(jù)。本文詳細(xì)闡述了此系統(tǒng)的設(shè)計(jì)方法，制作過程以及制作過程中的問題。設(shè)計(jì)者的工作包括：系統(tǒng)各部分電路元件的確定、確定系統(tǒng)框圖、畫出系統(tǒng)原理圖、根據(jù)原理圖設(shè)計(jì) FPGA 的 RTL代碼、綜合、仿真 RTL 代碼、設(shè)計(jì) PCB板和在線調(diào)試 FPGA 功能。 關(guān)鍵字： 數(shù)字鎖相環(huán)；幀同步；時(shí)分復(fù)用； Verilog HDL 語 言；串行 A/D 變換； 第 2 頁 共 63 頁 ____________________________________________________________________________________________________ Abstract The system is designed for data multiplexed and demultiplexed. It is based on TDM. The system includes the transmitter and the receiver. They are implemented mainly by FPGA. There are three inputs in the transmission system: data from A/D converter, DIP1 and DIP2. The three channels are out serially and timedivisional under the FPGA’s control. The FPGA in the transmitter is divided into four modules which are frequency divider, Barker generator, data multiplexer and voltage display. Voltage display is used for processing the data converted by ADC and sending it to the LED. The serial data are serial shifted into the FPGA in the receiver. Bitsynchronize and framesynchronize are both picked up, and then demultiplex. The FPGA in the receiver is divided into three modules which are digital PLL, data demultiplexer and voltage display. The transmitter will multiplex four ways of 8bit parallel data. The first way is ADC data, the second and the third way is generated by dipkey. The other is Barker code used for frame synchronizing. The receiver will maintain the bit synchronizing, recognize one frame and demultiplex three ways data. The essay will discuss the design progress, the programming idea and some problems. Works have to be done by the designer are: Specify all system ponents, Make system specification, Draw system schematics, Write RTL code according the schematics, Synthesis and simulate the RTL code, Design the PCBs, Validate the functions of the FPGA online. Keywords: DPLL。 Framesynchronize。 TDM。 Verilog HDL。 Serial A/D convert。 第 3 頁 共 63 頁 ____________________________________________________________________________________________________ 引言 1 1 數(shù)字復(fù)接系統(tǒng)簡(jiǎn)介 5 2 數(shù)字復(fù)接方法及方式 6 數(shù)字復(fù)接的方法 6 數(shù)字復(fù)接的方式 6 3 系統(tǒng)原理和各模塊設(shè)計(jì) 6 系統(tǒng)原理及框圖 6 發(fā)端系統(tǒng)設(shè)計(jì) 7 收端系統(tǒng)設(shè)計(jì) 9 FPGA 的 設(shè)計(jì)流程 11 設(shè)計(jì)輸入 11 設(shè)計(jì)綜合 12 仿真驗(yàn)證 12 設(shè)計(jì)實(shí)現(xiàn) 12 時(shí)序分析 12 發(fā)端 FPGA 設(shè)計(jì) 183
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