【正文】 is the ability to explore different possible system implementations (designspace exploration). Appropriate modeling can significantly shorten the design cycle of an ECS [2]. To overe the problems introduced by the heterogeneity of design models and tools, different methodologies and tools were developed [3]. These methodologies usually provide a means to create a uniform ECS model, simulate and evaluate its behavior, formally transform it towards an implementation, etc. control system design To improve and accelerate the traditional ECS design we propose the merging of these separated domains. On the basis of this merging, all the actors in the design process could better collaborate and exchange their data during the design process, they could do a more thorough designspace exploration and the design cycle could be made significantly shorter. Instead of developing a new methodology for ECS design, we propose to upgrade the traditional SWbased controlsystem design approach with efficient modeling and design of the HW platforms. Recently, several methodologies have been developed that concern HW/SW codesign. These methodologies enable the efficient design of SW and HW on embedded systems in terms of SW execution speed, HW resources usage, system flexibility, future upgradeability, final design costs, etc. We propose creating a formal bridge between the existing tools for controlscheduling codesign and HW/SW codesign. This bridge makes possible model transformations and the exchange of simulation results between tools for controlscheduling codesign and HW/SW codesign. The bridge is based on a formal transformation of models between different 河南科技大學(xué)本科畢業(yè)設(shè)計(jì)（論文） 5 design tools. Our foundation for the control scheduling codesign methodology is work presented in [4] and its associated tool, MoDEST, which is presented in [5]. For the purpose of HW/SW codesign we have selected the methodology presented in [6] with its associated abstractsystem modeling tool, ASyMod, which is presented in [7].With the bridge we are able to obtain more accurate controlperformance evaluations considering architectural details and even the possib ility to study mixed HW/SW implementations of the control system. Evaluating the impact of implementation in the early design stages reduces the number of designlifecycle iterations and shortens the time needed for a final calibration of the control laws. In the next section we present the related methodologies, followed by short descriptions of the MoDEST and ASyMod tools and their metamodels. In Section 3 we describe the formal rules for model transformation and the implementation of the bridge. In Section 4, two examples of an embedded controller are presented. By paring simulation results to measurements on a real implemented system, we show the benefits of our approach. Finally, the paper is concluded in Section 5. methodologies and tools The increasing need to optimize ECSs in terms of their control performance, RT constraints and cost efficiency has led to limited putational resources bined with their efficient exploitation and has, as a consequence, encouraged the emergence of new research areas. Domainspecific tools for controlscheduling codesign have been developed recently. These tools support implementation modeling and analysis in terms of control performance. Several of the tools are based on Matlab, which is traditionally used by control engineers for the design of control laws. The AIDA [8] toolset is a modelbased environment for the design and analysis of control systems, used either in standalone form or with Matlab. The toolset supports the 河南科技大學(xué)本科畢業(yè)設(shè)計(jì)（論文） 6 modeling of controlfunction execution on distributed HW ponents containing multiprocessors and munications links. The effects of the control algorithm‘s implementation on control performance can be analyzed. Jitterbug [9] is a Matlabbased analysis tool for puting a quadratic performance criterion in linear control systems under various timing conditions. Using Jitterbug, the sensitivity of control systems to delays, jitter and other interferences can be studied. The effects of different SW implementations on control performance can be analyzed. TrueTime [10] is a simulator in Matlab/Simulink designed for the cosimulation of the distributed controller‘s task execution on several RT kernels, work transmissions, and continuous plant dynamics. It provides a control performance analysis of distributed RT puterbased control systems, considering the effects of processors and work scheduling, task attributes, their data dependency, etc. TrueTime and Jitterbug can be used together to evaluate the performance of various control loop implementations [11]. Recently an ESMol [12] tool chain has been developed. It incorporates a prototype scheduling tool which calculates schedules for timetriggered works in distributed embedded systems. The ESMoL can be used together wit h the TrueTime in order to asses platform effects to puted schedule and to control performance. The research activities focused on software design for distributed realtime embedded systems lead to development several tools and languages. Timing Definition Language (TDL) is a highlevel description language for specifying the explicit timing requirements of a timetriggered application, which may be constructed out of several ponents. It promotes the idea that the functional and temporal behavior of developed software should be platform independent. This reduces costs of system integration, validation and maintenance. An automatic busschedule generation for messages over work topology is presented in [13]. An approach to optimize software ponent allocation systems on distributed realtime embedded systems is explained in [14]. Authors 河南科技大學(xué)本科