【正文】 ower consumption. The chip samples are implemented in a um process and tested in manual board.Figure. 1 TFT onechip driver IC diagram2. Structure of the driver ICGenerally, the driver IC is posed of a logic part, an analog part, and a memory part. The analog part is posed of the LCD driver, DCDC converter, voltage divider, and oscillator. The oscillator circuit generates a clock for display. The DCDC converter circuit receives the generated clock and generates the highest/lowest voltage level. The voltage divider circuit divides between the highest and lowest level. The driver block supplies the various voltages to the panel. Figure 1 is a block diagram of the implemented 260k TFT onechip IC. The 260k TFT onechip IC is posed of a logic, a merged memory, an oscillator, a DCDC converter block, a source/gate driver block and a mon voltage generating block. The logic part is posed of an MPU interface block, memoryaddressing block, and timing control block. The MPU interface block interfaces between the driver IC and the external MPU. The memoryaddressing block receives the decoded signal in the MPU interface and generates the memory address. The esister array is included in the gray scale generator. The implemented driving IC has three types of adjustment: a gradient adjustment, an amplitude adjustment, and a fine adjustment. The timing control block generates a signal, which controls the display panel. The gate driver block drives the gate on/off level voltage (VGH/VGOF). The each voltage generating block sequencely generates each voltage. (). The TFT panel must have a capacitor for storage. The driving method is a twotype per capacitor connection that is named the capacitor for storage in a TFT panel (CST) on the gate and the CST on the mon.The embedded memory is the same as normal memory. In addition, the embedded memory has the operation of accessing wholebit cells in the Xaddress. The output data from memory is transferred to the source driver. The source driver drives the panel with the voltage level, which is decoded by the accessed data. One time, the gate driver circuit selects one line of the panel. The next time, the gate driver circuit selects the next line, and the embedded memory transmits a wholebit cell in the next Xaddress. The gate driver circuit selects a nextcolumn line. With this accessing process, one line of the LCD panel is displayed.Figure. 2. Sequence of the voltage generatorFigure. 3. The proposed chip module3. Structure of graphic memoryThe embedded graphic SRAM is posed of a bit cell core block, I/O amp。 precharge block, a control block, a scan line decoding block, a wordline decoding block, a scan latch block, and several buffer blocks. The bit core block stores display data. The I/O amp。 precharge block controls charging and discharging of the bit/bitb line. The scan/word linedecoding block controls the wordline cell in the bit core block. This block accesses stored data and stores data. The scanlatch block does scan operations.The control block receives external write/read/scan enable signals from the addressgenerating block of the logic part and regenerates ram internal signals. The receivedorigin signal is transferred through a long metal line and the length of the metal line differs. Because of this, the writeenable signal of the most left wordline block can have a time gap with the most right wordline block. The slope of the external signal through the long metal line is low and the driven gate of the sloped signal consumes more power. If the origin signal is used without refining the I/O block and wordline block, the operation of the memory is unstable. Because of this instability, as the higher storage memory is embedded, regenerating the timing bees more important.The regenerated signal enables the access operation when the bit/bitb line is perfectly stable. The control block has an autodetect circuit, which detects the bit/bitb stable time. In the 8transistor graphic SRAM architecture, the read/write operation is the same as in a normal SRAM. However, a leaf cell has two additional transistors, which directly connect to the storage path. Because the additional two transistors are connected to the storage cell independently of the bit/bitb line, the 2transistor can independently access stored data.The additional transistor with a different access path makes