【正文】 h）如下所示。 `timescale 1 ns/ 1 ps module FIFO_vlg_tst()。 // constants // general purpose registers //reg eachvec。 // test vector input registers reg [7:0] IN。 reg RD_CLOCK。 reg RINC。 reg RRESET_N。 reg WINC。 reg WRESET_N。 reg WR_CLOCK。 // wires wire EMPTY_P。 wire FULL_P。 wire [7:0] OUT。 // assign statements (if any) FIFO i1 ( // port map connection between master ports and signals/registers .EMPTY_P(EMPTY_P), .FULL_P(FULL_P), .IN(IN), .OUT(OUT), .RD_CLOCK(RD_CLOCK), .RINC(RINC), .RRESET_N(RRESET_N), .WINC(WINC), .WRESET_N(WRESET_N), .WR_CLOCK(WR_CLOCK) )。 initial fork WR_CLOCK = 0。 WINC = 1。 10 WRESET_N = 0。 20 WRESET_N = 1。 40 WINC = 0。 //IN = 839。d10。 join initial fork RD_CLOCK = 0。 RINC = 1。 10 RRESET_N = 0。 200 RRESET_N = 1。 400 RINC = 0。 join always begin 10 WR_CLOCK = ~WR_CLOCK。 end always begin 100 RD_CLOCK = ~RD_CLOCK。 end endmodule B、綜合過程 將 RTL 文件拷如 liux 系統(tǒng)中進行綜合，生成門級網表，并根據(jù)要求來編寫約束文件，使文件最優(yōu)化。 完成后的約束文件如下： fifo constrains data authou johnny design entry read_verilog ../rtl/ check_design current_design set_max_area 1000 set_min_area setup operating conditions ,wire load, clocks,reset create_clock period 10 waveform{0 5} [get_ports CLOCK] create_clock period 20 [get_ports wclk] create_clock period 10 [get_ports rclk] set_dont_touch_work [get_clocks wclk] set_dont_touch_work [get_clocks rclk] set_dont_touch_work [list CLOCK RESET_N] set_operating_conditions max WCIND min WCCOM set_wire_load_model name 10x10 set_wire_load_mode enclosed set_clock_latency [get_clocks wclk] set_clock_latency [get_clocks rclk] set_clock_uncertainty setup hold [get_clocks wclk] set_clock_uncertainty setup hold [get_clocks rclk] useful mands report_port verbose report_clock reset_design list_libs remove_design all remove_design design list_fileslists all files in DC memory list_designs list_license input drives set_driving_cell lib_cell AN2 [get_ports wdata] set_drive 0 [list RESET_N] output load set_load 5 [all_outputs] set input amp。 set output delay set_input_delay max 10 clock wclk [get_ports wdata] set_input_delay max 5 clock rclk [get_ports rdata] set_output_delay max clock rclk [get_ports rdata] set_input_delay 5 clock CLOCK [all_inputs] Advanced constrints group_path set_false_path set_multicycle pile and write the database pile write hierarchy format verilog output ../rtl/ create reports write hierarchy format verilog output ../rtl/ write_sdc ../rtl/ report_timing report_area report_area ./ report_timing report_constraint all_violators gui_start report report_timing 結果 系統(tǒng)功能仿真波形： 時序仿真波形： 總結及感想 雖然該設計用了差不多 兩 個星期的時間，雖然效率不高，但也對學到了不少東西。對同 步異步信號有了較深的理解，以及怎樣通過看 RTL和描述語言作對比，找出問題的所在，此方法對于小的設計及有幫助。同時也讓我積累了一 些經驗， 比如在設計之前還查找相關的資料，了解該方面設計目前的大體情況。整理好設計方案、思想等。這樣能在很大程度上提高設計效率。 附件： 門級網表： module fifo ( wdata, full, winc, wclk, wrst_n, rdata, rinc, empty, rclk, rrst_n )。 input [8:0] wdata。 output [8:0] rdata。 input winc, wclk, wrst_n, rinc, rclk, rrst_n。 output full, empty。 wire N5, N6, \fifomem[0][7] , \fifomem[0][6] , \fifomem[0][5] , \fifomem[0][4] , \fifomem[0][3] , \fifomem[0][2] , \fifomem[0][1] , \fifomem[0][0] , \fifomem[1][7] , \fifomem[1][6] , \fifomem[1][5] , \fifomem[1][4] , \fifomem[1][3] , \fifomem[1][2] , \fifomem[1][1] , \fifomem[1][0] , \fifomem[2][7] , \fifomem[2][6] , \fifomem[2][5] , \fifomem[2][4] , \fifomem[2][3] , \fifomem[2][2] , \fifomem[2][1] , \fifomem[2][0] , \fifomem[3][7] , \fifomem[3][6] , \fifomem[3][5] , \fifomem[3][4] , \fifomem[3][3] , \fifomem[3][2] , \fifomem[3][1] , \fifomem[3][0] , N14, N15, N16, N17, N18, N19, N20, N21, \w2_rptr[2] , full_val, \rbin[2] , empty_val, n10, n20, n23, n26, n29, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n96, n97, n98, n99, n100, n101, n102, n103, n104, n105, n106, n107, n108, n109, n110, n111, n112, n113, n114, n115, n116, n117, n118, n119, n120, n121, n122, n123, n124, n125, n126, n127, \dp_cluster_0/N34 , N32, \dp_cluster_1/N36 , N31, n128, n129, n130, n131, n132, n133, n134, n135, n136, n137, n138, n139, n140, n141, n142, n143, n144, n145, n146, n147, n148, n149, n150, n151, n152, n153, n154, n155, n156, n157, n158, n159, n160, n161, n162, n163, n164, n165, n166, n167, n168, n169, n170, n171, n172, n173, n174, n175,